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[AArch64] Correct SCVTF/UCVTF instructions for vector input #152974

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Sep 12, 2025
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[AArch64] Correct SCVTF/UCVTF instructions for vector input #152974

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e82a221
[AArch64] Correct SCVTF/UCVTF instructions for vector inputs
Amichaxx Aug 11, 2025
e3cced3
Add isel patterns for SCVTF/UCVTF
Amichaxx Aug 20, 2025
675d79d
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Amichaxx Sep 9, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5520,6 +5520,11 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
let Inst{31} = 1; // 64-bit FPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
def : Pat<(v1f64 (extract_subvector (v2f64 (node (v2i64 (sext (v2i32 V64:$Rn))))), (i64 0))),
(!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V64:$Rn, ssub))>;

def : Pat<(v1f64 (extract_subvector (v2f64 (node (v2i64 (zext (v2i32 V64:$Rn))))), (i64 0))),
(!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V64:$Rn, ssub))>;

def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
(!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG V128:$Rn, ssub))>;
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22 changes: 4 additions & 18 deletions llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll
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Expand Up @@ -94,16 +94,10 @@ define double @scvtf_f64i32_neg(<4 x i32> %x) {
ret double %conv
}

; This test does not give the indended result of scvtf d0, s0
; This is due to the input being loaded as a 2 item vector and
; therefore using vector inputs that do not match the pattern
; This test will be fixed in a future revision
define <1 x double> @scvtf_f64i32_simple(<1 x i32> %x) {
; CHECK-LABEL: scvtf_f64i32_simple:
; CHECK: // %bb.0:
; CHECK-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-NEXT: scvtf v0.2d, v0.2d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: scvtf d0, s0
; CHECK-NEXT: ret
;
; CHECK-NO-FPRCVT-LABEL: scvtf_f64i32_simple:
Expand Down Expand Up @@ -202,10 +196,8 @@ define float @scvtf_f32i64_neg(<2 x i64> %x) {
ret float %conv
}

; This test does not give the indended result of scvtf s0, d0
; This is due to the input being loaded as a 2 item vector and
; therefore using vector inputs that do not match the pattern
; This test will be fixed in a future revision
; <1 x float> is illegal on AArch64 and is widened to <2 x float>.
; This widening introduces the extra insert/extract/zeroing instructions.
define <1 x float> @scvtf_f32i64_simple(<1 x i64> %x) {
; CHECK-LABEL: scvtf_f32i64_simple:
; CHECK: // %bb.0:
Expand Down Expand Up @@ -315,16 +307,10 @@ define double @ucvtf_f64i32_neg(<4 x i32> %x) {
ret double %conv
}

; This test does not give the indended result of ucvtf d0, s0
; This is due to the input being loaded as a 2 item vector and
; therefore using vector inputs that do not match the pattern
; This test will be fixed in a future revision
define <1 x double> @ucvtf_f64i32_simple(<1 x i32> %x) {
; CHECK-LABEL: ucvtf_f64i32_simple:
; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: ucvtf v0.2d, v0.2d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ucvtf d0, s0
; CHECK-NEXT: ret
;
; CHECK-NO-FPRCVT-LABEL: ucvtf_f64i32_simple:
Expand Down