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Aug 12, 2025
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AMDGPU/GlobalISel: Switch a few tests to new-reg-bank-select #153174

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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_ADD_LSHL_U32
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=WAVE64 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=WAVE32 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=WAVE64 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=WAVE32 %s

define i32 @s_andn2_i1_vcc(i32 %arg0, i32 %arg1) {
; WAVE64-LABEL: s_andn2_i1_vcc:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s

define hidden <2 x i64> @icmp_v2i32_sext_to_v2i64(<2 x i32> %arg) {
; CHECK-LABEL: icmp_v2i32_sext_to_v2i64:
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16 changes: 10 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=WAVE64 %s
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefix=WAVE32 %s
; RUN: llc -global-isel -new-reg-bank-select -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=WAVE64 %s
; RUN: llc -global-isel -new-reg-bank-select -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefix=WAVE32 %s

; This was mishandling the constant true and false values used as a
; scalar branch condition.
Expand Down Expand Up @@ -76,7 +76,8 @@ define void @br_undef() {
; WAVE64-NEXT: .LBB2_1: ; %bb0
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
; WAVE64-NEXT: ; implicit-def: $sgpr4
; WAVE64-NEXT: s_and_b32 s4, s4, 1
; WAVE64-NEXT: s_mov_b32 s5, 1
; WAVE64-NEXT: s_and_b32 s4, s4, s5
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
; WAVE64-NEXT: s_cbranch_scc1 .LBB2_1
; WAVE64-NEXT: ; %bb.2: ; %.exit5
Expand All @@ -88,7 +89,8 @@ define void @br_undef() {
; WAVE32-NEXT: .LBB2_1: ; %bb0
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
; WAVE32-NEXT: ; implicit-def: $sgpr4
; WAVE32-NEXT: s_and_b32 s4, s4, 1
; WAVE32-NEXT: s_mov_b32 s5, 1
; WAVE32-NEXT: s_and_b32 s4, s4, s5
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
; WAVE32-NEXT: s_cbranch_scc1 .LBB2_1
; WAVE32-NEXT: ; %bb.2: ; %.exit5
Expand All @@ -110,7 +112,8 @@ define void @br_poison() {
; WAVE64-NEXT: .LBB3_1: ; %bb0
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
; WAVE64-NEXT: ; implicit-def: $sgpr4
; WAVE64-NEXT: s_and_b32 s4, s4, 1
; WAVE64-NEXT: s_mov_b32 s5, 1
; WAVE64-NEXT: s_and_b32 s4, s4, s5
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
; WAVE64-NEXT: s_cbranch_scc1 .LBB3_1
; WAVE64-NEXT: ; %bb.2: ; %.exit5
Expand All @@ -122,7 +125,8 @@ define void @br_poison() {
; WAVE32-NEXT: .LBB3_1: ; %bb0
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
; WAVE32-NEXT: ; implicit-def: $sgpr4
; WAVE32-NEXT: s_and_b32 s4, s4, 1
; WAVE32-NEXT: s_mov_b32 s5, 1
; WAVE32-NEXT: s_and_b32 s4, s4, s5
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
; WAVE32-NEXT: s_cbranch_scc1 .LBB3_1
; WAVE32-NEXT: ; %bb.2: ; %.exit5
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s

define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_1:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s

define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_and_1:
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