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[mlir][xegpu] Add definitons of MatrixDescType and related ops. #153273
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@@ -201,4 +201,53 @@ def XeGPU_Nbarrier: XeGPUTypeDef<"Nbarrier", "nbarrier", [], "mlir::Type"> { | |
}]; | ||
} | ||
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def XeGPU_MemDesc: XeGPUTypeDef<"MemDesc", "mem_desc", [ShapedTypeInterface], "mlir::Type"> { | ||
let summary = "MemDesc describing the data in SLM"; | ||
let description = [{ | ||
MemDesc represents a block of data stored in shared local memory. | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. consider "a block of data" => "multi-dimensional array buffer". MemDesc associates "structure" information to the buffer (block of data) so it can be viewed as multi-dimension array buffer. |
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By default, unless a layout attribute is provided, the data is stored | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. What is this layout? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. In the tests, there is usage like There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Please refer to intel/mlir-extensions#1092 for the motivation and explanation of the slm memory layout of matrix descriptor. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. +1 to the questions here. It just reads as a MemRef layout which is fine but could use explicit clarification as Could you add more description here? Or at least an example snippet. |
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contiguously in row-major order within the region. | ||
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Examples: | ||
```mlir | ||
// A block of data stored in column-major order. | ||
!xegpu.mem_desc<128x128xf16, #xegpu.mem_layout<stride = [1, 128]>> | ||
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// A block of data stored in a blocked layout. Elements within the same block | ||
// are stored contiguously in memory. Blocks are stored in row-major order. | ||
!xegpu.mem_desc<128x128xf16, #xegpu.mem_layout<block = [8, 8]>> | ||
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// A block of data stored in column-major order with blocked layout. | ||
!xegpu.mem_desc<128x128xf16, #xegpu.mem_layout<stride = [1, 128], block = [8, 8]>> | ||
``` | ||
}]; | ||
let parameters = (ins ArrayRefParameter<"int64_t">: $shape, | ||
"mlir::Type": $elementType, | ||
OptionalParameter<"MemLayoutAttr">: $mem_layout); | ||
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let extraClassDeclaration = [{ | ||
bool hasRank() const { return true; } | ||
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MemDescType cloneWith(std::optional<llvm::ArrayRef<int64_t>> shape, Type elementType) const { | ||
return MemDescType::get(getContext(), shape.value_or(getShape()), elementType, getMemLayout()); | ||
} | ||
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ArrayAttr getStrides() { | ||
auto layout = getMemLayout(); | ||
if (layout && layout.hasAttr("stride")) { | ||
return layout.getStrides(); | ||
} | ||
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// derive and return default strides | ||
SmallVector<int64_t> defaultStrides; | ||
llvm::append_range(defaultStrides, getShape().drop_front()); | ||
llvm::append_values(defaultStrides, 1); | ||
Builder builder(getContext()); | ||
return builder.getI64ArrayAttr(defaultStrides); | ||
} | ||
}]; | ||
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let hasCustomAssemblyFormat = true; | ||
} | ||
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#endif // MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD |
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nit: remove extra line