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[AArch64] Run CSE after conversion from flag-setting variants to non-flag setting variants #153316

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[AArch64] Run CSE after conversion from flag-setting variants to non-flag setting variants #153316

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63225d0
[AArch64] Run CSE one last time
AZero13 Aug 12, 2025
9a04ea7
Update atomic-ops-lse.ll
AZero13 Aug 13, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -788,8 +788,21 @@ void AArch64PassConfig::addMachineSSAOptimization() {
// Run default MachineSSAOptimization first.
TargetPassConfig::addMachineSSAOptimization();

// With optimization, dead code should already be eliminated. However
// there is one known exception: peephole optimizations may open more
// opportunities for dead code. This is especially true for targets whose
// peephole optimizations like ARM and AArch64 where dead defs to the flag
// register are removed, which previously prevented CSE.
addPass(&MachineCSELegacyID);
addPass(&MachineSinkingLegacyID);

if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createAArch64MIPeepholeOptPass());

// Clean-up any last code that can be eliminated
// Due to the fact that the demotion of some instructions
// can result in the removal of instructions previously unable to be removed
addPass(&DeadMachineInstructionElimID);
}

bool AArch64PassConfig::addILPOpts() {
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AArch64/O3-pipeline.ll
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Expand Up @@ -162,6 +162,8 @@
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: AArch64 MI Peephole Optimization pass
; CHECK-NEXT: AArch64 Dead register definitions
; CHECK-NEXT: Machine Common Subexpression Elimination
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: Detect Dead Lanes
; CHECK-NEXT: Init Undef Pass
; CHECK-NEXT: Process Implicit Definitions
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78 changes: 36 additions & 42 deletions llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
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Expand Up @@ -206,13 +206,12 @@ define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) {
; CHECK-LABEL: insert_vec_v8i16_uaddlv_from_v8i16:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
; CHECK-NEXT: uaddlv.8h s0, v0
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: str q1, [x0]
; CHECK-NEXT: uaddlv.8h s1, v0
; CHECK-NEXT: mov.h v0[0], v1[0]
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret

entry:
Expand All @@ -228,14 +227,13 @@ define void @insert_vec_v3i16_uaddlv_from_v8i16(ptr %0) {
; CHECK-LABEL: insert_vec_v3i16_uaddlv_from_v8i16:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: add x8, x0, #8
; CHECK-NEXT: uaddlv.8h s0, v0
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: st1.s { v1 }[2], [x8]
; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: uaddlv.8h s1, v0
; CHECK-NEXT: mov.h v0[0], v1[0]
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: st1.s { v0 }[2], [x8]
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret

entry:
Expand Down Expand Up @@ -283,9 +281,9 @@ define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) {
; CHECK-NEXT: stp q0, q0, [x0, #32]
; CHECK-NEXT: mov.h v2[0], v1[0]
; CHECK-NEXT: bic.4h v2, #255, lsl #8
; CHECK-NEXT: ushll.4s v2, v2, #0
; CHECK-NEXT: ucvtf.4s v2, v2
; CHECK-NEXT: stp q2, q0, [x0]
; CHECK-NEXT: ushll.4s v1, v2, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: stp q1, q0, [x0]
; CHECK-NEXT: ret

entry:
Expand Down Expand Up @@ -386,12 +384,11 @@ define void @insert_vec_v4i16_uaddlv_from_v4i32(ptr %0) {
; CHECK-LABEL: insert_vec_v4i16_uaddlv_from_v4i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: uaddlv.4s d0, v0
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: str q1, [x0]
; CHECK-NEXT: uaddlv.4s d1, v0
; CHECK-NEXT: mov.h v0[0], v1[0]
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret

entry:
Expand All @@ -407,14 +404,13 @@ define void @insert_vec_v16i16_uaddlv_from_v4i32(ptr %0) {
; CHECK-LABEL: insert_vec_v16i16_uaddlv_from_v4i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: uaddlv.4s d0, v0
; CHECK-NEXT: stp q2, q2, [x0, #32]
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: uaddlv.4s d1, v0
; CHECK-NEXT: stp q0, q0, [x0, #32]
; CHECK-NEXT: mov.h v2[0], v1[0]
; CHECK-NEXT: ushll.4s v1, v2, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: stp q1, q2, [x0]
; CHECK-NEXT: stp q1, q0, [x0]
; CHECK-NEXT: ret

entry:
Expand All @@ -430,14 +426,13 @@ define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) {
; CHECK-LABEL: insert_vec_v8i8_uaddlv_from_v4i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
; CHECK-NEXT: uaddlv.4s d0, v0
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: bic.4h v1, #255, lsl #8
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: str q1, [x0]
; CHECK-NEXT: uaddlv.4s d1, v0
; CHECK-NEXT: mov.h v0[0], v1[0]
; CHECK-NEXT: bic.4h v0, #255, lsl #8
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret

entry:
Expand All @@ -453,15 +448,14 @@ define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {
; CHECK-LABEL: insert_vec_v16i8_uaddlv_from_v4i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: uaddlv.4s d0, v0
; CHECK-NEXT: stp q2, q2, [x0, #32]
; CHECK-NEXT: mov.h v1[0], v0[0]
; CHECK-NEXT: bic.4h v1, #255, lsl #8
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: uaddlv.4s d1, v0
; CHECK-NEXT: stp q0, q0, [x0, #32]
; CHECK-NEXT: mov.h v2[0], v1[0]
; CHECK-NEXT: bic.4h v2, #255, lsl #8
; CHECK-NEXT: ushll.4s v1, v2, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: stp q1, q2, [x0]
; CHECK-NEXT: stp q1, q0, [x0]
; CHECK-NEXT: ret

entry:
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6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AArch64/addsub-shifted-reg-cheap-as-move.ll
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Expand Up @@ -97,15 +97,13 @@ define void @f1(i1 %c0, i1 %c1, ptr %a, i64 %i) {
; LSLFAST-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; LSLFAST-NEXT: .cfi_def_cfa_offset 16
; LSLFAST-NEXT: .cfi_offset w30, -16
; LSLFAST-NEXT: add x8, x2, x3, lsl #4
; LSLFAST-NEXT: add x0, x2, x3, lsl #4
; LSLFAST-NEXT: tbz w1, #0, .LBB1_3
; LSLFAST-NEXT: // %bb.2: // %B
; LSLFAST-NEXT: mov x0, x8
; LSLFAST-NEXT: bl g
; LSLFAST-NEXT: b .LBB1_4
; LSLFAST-NEXT: .LBB1_3: // %C
; LSLFAST-NEXT: add x0, x2, x3, lsl #4
; LSLFAST-NEXT: mov x1, x8
; LSLFAST-NEXT: mov x1, x0
; LSLFAST-NEXT: bl g
; LSLFAST-NEXT: .LBB1_4:
; LSLFAST-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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