Skip to content

[AMDGPU] Add HW_REG_IB_STS2 on gfx1250 #153479

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
rampitec merged 3 commits into from
Aug 14, 2025
Merged

[AMDGPU] Add HW_REG_IB_STS2 on gfx1250 #153479

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
d2854ea
[AMDGPU] Add HW_REG_IB_STS2 on gfx1250
rampitec Aug 13, 2025
d6a7091
Merge branch 'main' into users/rampitec/08-13-_amdgpu_add_hw_reg_ib_s…
rampitec Aug 13, 2025
5c497c6
Merge branch 'main' into users/rampitec/08-13-_amdgpu_add_hw_reg_ib_s…
rampitec Aug 14, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIDefines.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -513,6 +513,7 @@ enum Id { // HwRegCode, (6) [5:0]
ID_HW_ID2 = 24,
ID_POPS_PACKER = 25,
ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
ID_IB_STS2 = 28,
ID_SHADER_CYCLES = 29,
ID_SHADER_CYCLES_HI = 30,
ID_DVGPR_ALLOC_LO = 31,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ static constexpr CustomOperand Operands[] = {
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{{""}},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
{{""}},
{{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
{{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
{{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/AMDGPU/gfx1250_asm_operands.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,3 +52,7 @@ s_setreg_b32 hwreg(34), s1
s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1
// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU
// GFX1250: encoding: [0x22,0xf8,0x01,0xb9]

s_setreg_b32 hwreg(HW_REG_IB_STS2), s1
// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU
// GFX1250: encoding: [0x1c,0xf8,0x01,0xb9]
3 changes: 3 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -32,3 +32,6 @@

# GFX1250: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 ; encoding: [0x22,0xf8,0x01,0xb9]
0x22,0xf8,0x01,0xb9

# GFX1250: s_setreg_b32 hwreg(HW_REG_IB_STS2), s1 ; encoding: [0x1c,0xf8,0x01,0xb9]
0x1c,0xf8,0x01,0xb9