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[RISCV] Remove experimental from Smctr and Ssctr. #153903

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Merged
merged 1 commit into from
Aug 16, 2025
Merged

[RISCV] Remove experimental from Smctr and Ssctr. #153903

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4 changes: 2 additions & 2 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -128,6 +128,7 @@
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
Expand All @@ -140,6 +141,7 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
Expand Down Expand Up @@ -214,8 +216,6 @@
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension)
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -118,6 +118,7 @@ Changes to the RISC-V Backend
* `llvm-objdump` now has basic support for switching between disassembling code
and data using mapping symbols such as `$x` and `$d`. Switching architectures
using `$x` with an architecture string suffix is not yet supported.
* Ssctr and Smctr extensions are no longer experimental.

Changes to the WebAssembly Backend
----------------------------------
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12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -1055,13 +1055,13 @@ def FeatureStdExtSupm
"Indicates User-mode Pointer Masking">;

def FeatureStdExtSmctr
: RISCVExperimentalExtension<1, 0,
"Control Transfer Records Machine Level",
[FeatureStdExtSscsrind]>;
: RISCVExtension<1, 0,
"Control Transfer Records Machine Level",
[FeatureStdExtSscsrind]>;
def FeatureStdExtSsctr
: RISCVExperimentalExtension<1, 0,
"Control Transfer Records Supervisor Level",
[FeatureStdExtSscsrind]>;
: RISCVExtension<1, 0,
"Control Transfer Records Supervisor Level",
[FeatureStdExtSscsrind]>;
def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),
"'Smctr' (Control Transfer Records Machine Level) or "
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -173,8 +173,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s

; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
Expand Down Expand Up @@ -336,8 +336,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/features-info.ll
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Expand Up @@ -27,8 +27,6 @@
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK-NEXT: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves).
; CHECK-NEXT: experimental-xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension).
Expand Down Expand Up @@ -145,6 +143,7 @@
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
; CHECK-NEXT: smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).
; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode).
Expand All @@ -157,6 +156,7 @@
; CHECK-NEXT: sscofpmf - 'Sscofpmf' (Count Overflow and Mode-Based Filtering).
; CHECK-NEXT: sscounterenw - 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero).
; CHECK-NEXT: sscsrind - 'Sscsrind' (Indirect CSR Access Supervisor Level).
; CHECK-NEXT: ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK-NEXT: ssdbltrp - 'Ssdbltrp' (Double Trap Supervisor Level).
; CHECK-NEXT: ssnpm - 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode).
; CHECK-NEXT: sspm - 'Sspm' (Indicates Supervisor-mode Pointer Masking).
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/MC/RISCV/smctr-ssctr-valid.s
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@@ -1,22 +1,22 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-smctr -M no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+smctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-smctr -M no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv64 -mattr=+smctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ssctr -M no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+ssctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ssctr -M no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv64 -mattr=+ssctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-smctr < %s \
# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smctr < %s \
# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-smctr < %s \
# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smctr < %s \
# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-ssctr < %s \
# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+ssctr < %s \
# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-ssctr < %s \
# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+ssctr < %s \
# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s

# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \
Expand Down
4 changes: 2 additions & 2 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1099,6 +1099,7 @@ R"(All available -march extensions for RISC-V
smcdeleg 1.0
smcntrpmf 1.0
smcsrind 1.0
smctr 1.0
smdbltrp 1.0
smepmp 1.0
smmpm 1.0
Expand All @@ -1111,6 +1112,7 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
ssctr 1.0
ssdbltrp 1.0
ssnpm 1.0
sspm 1.0
Expand Down Expand Up @@ -1185,8 +1187,6 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
zvqdotq 0.0
smctr 1.0
ssctr 1.0
svukte 0.3
xqccmp 0.3
xqcia 0.7
Expand Down
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