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7 changes: 7 additions & 0 deletions llvm/include/llvm/IR/PatternMatch.h
Original file line number Diff line number Diff line change
Expand Up @@ -2193,6 +2193,13 @@ m_TruncOrSelf(const OpTy &Op) {
return m_CombineOr(m_Trunc(Op), Op);
}

template <typename OpTy>
inline match_combine_or<NoWrapTrunc_match<OpTy, TruncInst::NoUnsignedWrap>,
OpTy>
m_NUWTruncOrSelf(const OpTy &Op) {
return m_CombineOr(m_NUWTrunc(Op), Op);
}

/// Matches SExt.
template <typename OpTy>
inline CastInst_match<OpTy, SExtInst> m_SExt(const OpTy &Op) {
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6 changes: 5 additions & 1 deletion llvm/lib/IR/IntrinsicInst.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -613,8 +613,12 @@ bool VPIntrinsic::canIgnoreVectorLengthParam() const {
if (EC.isScalable()) {
// Compare vscale patterns
uint64_t VScaleFactor;
if (match(VLParam, m_Mul(m_VScale(), m_ConstantInt(VScaleFactor))))
if (match(VLParam, m_NUWTruncOrSelf(
m_NUWMul(m_VScale(), m_ConstantInt(VScaleFactor)))))
return VScaleFactor >= EC.getKnownMinValue();
if (match(VLParam, m_NUWTruncOrSelf(
m_NUWShl(m_VScale(), m_ConstantInt(VScaleFactor)))))
return 1 << VScaleFactor >= EC.getKnownMinValue();
return (EC.getKnownMinValue() == 1) && match(VLParam, m_VScale());
}

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107 changes: 107 additions & 0 deletions llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp-convert-evl.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,107 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=pre-isel-intrinsic-lowering -expandvp-override-evl-transform=Convert -expandvp-override-mask-transform=Legal -S < %s | FileCheck %s

define <vscale x 2 x i64> @unknown_evl(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %evl) {
; CHECK-LABEL: define <vscale x 2 x i64> @unknown_evl(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]], i32 [[EVL:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 [[EVL]])
; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 2 x i1> [[TMP1]], [[M]]
; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 2
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[TMP2]], i32 [[SCALABLE_SIZE]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}

define <2 x i64> @exact_evl_fixed(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: define <2 x i64> @exact_evl_fixed(
; CHECK-SAME: <2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], <2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[ADD:%.*]] = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> [[M]], i32 2)
; CHECK-NEXT: ret <2 x i64> [[ADD]]
;
%add = call <2 x i64> @llvm.vp.add(<2 x i64> poison, <2 x i64> poison, <2 x i1> %m, i32 2)
ret <2 x i64> %add
}

define <vscale x 2 x i64> @exact_evl_vscale_mul(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: define <vscale x 2 x i64> @exact_evl_vscale_mul(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[EVL:%.*]] = mul nuw i32 [[VSCALE]], 2
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[M]], i32 [[EVL]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%vscale = call i32 @llvm.vscale()
%evl = mul nuw i32 %vscale, 2
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}

define <vscale x 2 x i64> @exact_evl_vscale_shl(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: define <vscale x 2 x i64> @exact_evl_vscale_shl(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[EVL:%.*]] = shl nuw i32 [[VSCALE]], 1
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[M]], i32 [[EVL]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%vscale = call i32 @llvm.vscale()
%evl = shl nuw i32 %vscale, 1
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}

define <vscale x 2 x i64> @exact_evl_vscale_mul_trunc(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: define <vscale x 2 x i64> @exact_evl_vscale_mul_trunc(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHL:%.*]] = mul nuw i64 [[VSCALE]], 2
; CHECK-NEXT: [[EVL:%.*]] = trunc nuw i64 [[SHL]] to i32
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[M]], i32 [[EVL]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%vscale = call i64 @llvm.vscale()
%shl = mul nuw i64 %vscale, 2
%evl = trunc nuw i64 %shl to i32
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}


define <vscale x 2 x i64> @exact_evl_vscale_shl_trunc(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: define <vscale x 2 x i64> @exact_evl_vscale_shl_trunc(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[VSCALE]], 1
; CHECK-NEXT: [[EVL:%.*]] = trunc nuw i64 [[SHL]] to i32
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[M]], i32 [[EVL]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%vscale = call i64 @llvm.vscale()
%shl = shl nuw i64 %vscale, 1
%evl = trunc nuw i64 %shl to i32
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}

define <vscale x 2 x i64> @exact_evl_vscale_shl_trunc_no_nuw(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: define <vscale x 2 x i64> @exact_evl_vscale_shl_trunc_no_nuw(
; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]], <vscale x 2 x i64> [[Y:%.*]], <vscale x 2 x i1> [[M:%.*]]) {
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[VSCALE]], 1
; CHECK-NEXT: [[EVL:%.*]] = trunc i64 [[SHL]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 [[EVL]])
; CHECK-NEXT: [[TMP2:%.*]] = and <vscale x 2 x i1> [[TMP1]], [[M]]
; CHECK-NEXT: [[VSCALE1:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE1]], 2
; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> [[TMP2]], i32 [[SCALABLE_SIZE]])
; CHECK-NEXT: ret <vscale x 2 x i64> [[ADD]]
;
%vscale = call i64 @llvm.vscale()
%shl = shl nuw i64 %vscale, 1
%evl = trunc i64 %shl to i32
%add = call <vscale x 2 x i64> @llvm.vp.add(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %add
}
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