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JanekvO merged 2 commits into from
Aug 20, 2025
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[AMDGPU][NFC] Enable gfx942 for more tests #154363

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60f026d
[AMDGPU][NFC] Enable gfx942 for more tests
JanekvO Aug 19, 2025
09d0e3f
Cut down irrelevant tests
JanekvO Aug 20, 2025
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3,519 changes: 3,519 additions & 0 deletions llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
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1,211 changes: 1,211 additions & 0 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
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2,519 changes: 2,519 additions & 0 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
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1,270 changes: 1,270 additions & 0 deletions llvm/test/CodeGen/AMDGPU/bypass-div.ll
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907 changes: 907 additions & 0 deletions llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
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220 changes: 148 additions & 72 deletions llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX942 %s

define amdgpu_kernel void @select_and1(ptr addrspace(1) %p, i32 %x, i32 %y) {
; GCN-LABEL: select_and1:
Expand Down Expand Up @@ -56,24 +57,43 @@ define amdgpu_kernel void @select_and3(ptr addrspace(1) %p, i32 %x, i32 %y) {
}

define amdgpu_kernel void @select_and_v4(ptr addrspace(1) %p, i32 %x, <4 x i32> %y) {
; GCN-LABEL: select_and_v4:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s8, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_gt_i32 s8, 10
; GCN-NEXT: s_cselect_b32 s3, s3, 0
; GCN-NEXT: s_cselect_b32 s2, s2, 0
; GCN-NEXT: s_cselect_b32 s1, s1, 0
; GCN-NEXT: s_cselect_b32 s0, s0, 0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GCN-NEXT: s_endpgm
; GFX9-LABEL: select_and_v4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s8, s[4:5], 0x2c
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_gt_i32 s8, 10
; GFX9-NEXT: s_cselect_b32 s3, s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s2, 0
; GFX9-NEXT: s_cselect_b32 s1, s1, 0
; GFX9-NEXT: s_cselect_b32 s0, s0, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX9-NEXT: s_endpgm
;
; GFX942-LABEL: select_and_v4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s8, s[4:5], 0x2c
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_cmp_gt_i32 s8, 10
; GFX942-NEXT: s_cselect_b32 s3, s3, 0
; GFX942-NEXT: s_cselect_b32 s2, s2, 0
; GFX942-NEXT: s_cselect_b32 s1, s1, 0
; GFX942-NEXT: s_cselect_b32 s0, s0, 0
; GFX942-NEXT: v_mov_b32_e32 v2, s0
; GFX942-NEXT: v_mov_b32_e32 v3, s1
; GFX942-NEXT: v_mov_b32_e32 v4, s2
; GFX942-NEXT: v_mov_b32_e32 v5, s3
; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
%c = icmp slt i32 %x, 11
%s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
%a = and <4 x i32> %s, %y
Expand Down Expand Up @@ -136,24 +156,43 @@ define amdgpu_kernel void @select_or3(ptr addrspace(1) %p, i32 %x, i32 %y) {
}

define amdgpu_kernel void @select_or_v4(ptr addrspace(1) %p, i32 %x, <4 x i32> %y) {
; GCN-LABEL: select_or_v4:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s8, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lt_i32 s8, 11
; GCN-NEXT: s_cselect_b32 s3, s3, -1
; GCN-NEXT: s_cselect_b32 s2, s2, -1
; GCN-NEXT: s_cselect_b32 s1, s1, -1
; GCN-NEXT: s_cselect_b32 s0, s0, -1
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GCN-NEXT: s_endpgm
; GFX9-LABEL: select_or_v4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s8, s[4:5], 0x2c
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_lt_i32 s8, 11
; GFX9-NEXT: s_cselect_b32 s3, s3, -1
; GFX9-NEXT: s_cselect_b32 s2, s2, -1
; GFX9-NEXT: s_cselect_b32 s1, s1, -1
; GFX9-NEXT: s_cselect_b32 s0, s0, -1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX9-NEXT: s_endpgm
;
; GFX942-LABEL: select_or_v4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s8, s[4:5], 0x2c
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_cmp_lt_i32 s8, 11
; GFX942-NEXT: s_cselect_b32 s3, s3, -1
; GFX942-NEXT: s_cselect_b32 s2, s2, -1
; GFX942-NEXT: s_cselect_b32 s1, s1, -1
; GFX942-NEXT: s_cselect_b32 s0, s0, -1
; GFX942-NEXT: v_mov_b32_e32 v2, s0
; GFX942-NEXT: v_mov_b32_e32 v3, s1
; GFX942-NEXT: v_mov_b32_e32 v4, s2
; GFX942-NEXT: v_mov_b32_e32 v5, s3
; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
%c = icmp slt i32 %x, 11
%s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
%a = or <4 x i32> %s, %y
Expand Down Expand Up @@ -236,23 +275,41 @@ define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(ptr ad
}

define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(ptr addrspace(1) %p, i1 %cond) {
; GCN-LABEL: sel_constants_sub_constant_sel_constants_v4i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bitcmp1_b32 s2, 0
; GCN-NEXT: s_cselect_b32 s2, 7, 14
; GCN-NEXT: s_cselect_b32 s3, 6, 10
; GCN-NEXT: s_cselect_b32 s4, 5, 6
; GCN-NEXT: s_cselect_b32 s5, 9, 2
; GCN-NEXT: v_mov_b32_e32 v0, s5
; GCN-NEXT: v_mov_b32_e32 v1, s4
; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: v_mov_b32_e32 v3, s2
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GCN-NEXT: s_endpgm
; GFX9-LABEL: sel_constants_sub_constant_sel_constants_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bitcmp1_b32 s2, 0
; GFX9-NEXT: s_cselect_b32 s2, 7, 14
; GFX9-NEXT: s_cselect_b32 s3, 6, 10
; GFX9-NEXT: s_cselect_b32 s4, 5, 6
; GFX9-NEXT: s_cselect_b32 s5, 9, 2
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX942-LABEL: sel_constants_sub_constant_sel_constants_v4i32:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_bitcmp1_b32 s2, 0
; GFX942-NEXT: s_cselect_b32 s2, 7, 14
; GFX942-NEXT: s_cselect_b32 s3, 6, 10
; GFX942-NEXT: s_cselect_b32 s4, 5, 6
; GFX942-NEXT: s_cselect_b32 s5, 9, 2
; GFX942-NEXT: v_mov_b32_e32 v2, s5
; GFX942-NEXT: v_mov_b32_e32 v3, s4
; GFX942-NEXT: v_mov_b32_e32 v4, s3
; GFX942-NEXT: v_mov_b32_e32 v5, s2
; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1]
; GFX942-NEXT: s_endpgm
%sel = select i1 %cond, <4 x i32> <i32 -4, i32 2, i32 3, i32 4>, <4 x i32> <i32 3, i32 1, i32 -1, i32 -3>
%bo = sub <4 x i32> <i32 5, i32 7, i32 9, i32 11>, %sel
store <4 x i32> %bo, ptr addrspace(1) %p, align 32
Expand Down Expand Up @@ -461,24 +518,43 @@ define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(ptr addrspace(1) %p
}

define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(ptr addrspace(1) %p, i1 %cond) {
; GCN-LABEL: fsub_constant_sel_constants_v4f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: s_mov_b32 s3, 0x41500000
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bitcmp1_b32 s2, 0
; GCN-NEXT: s_cselect_b32 s2, s3, 0x40c00000
; GCN-NEXT: s_cselect_b32 s3, 0x41100000, 4.0
; GCN-NEXT: s_cselect_b32 s4, 0x40a00000, 2.0
; GCN-NEXT: s_cselect_b32 s5, 1.0, 0
; GCN-NEXT: v_mov_b32_e32 v0, s5
; GCN-NEXT: v_mov_b32_e32 v1, s4
; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: v_mov_b32_e32 v3, s2
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GCN-NEXT: s_endpgm
; GFX9-LABEL: fsub_constant_sel_constants_v4f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0x41500000
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bitcmp1_b32 s2, 0
; GFX9-NEXT: s_cselect_b32 s2, s3, 0x40c00000
; GFX9-NEXT: s_cselect_b32 s3, 0x41100000, 4.0
; GFX9-NEXT: s_cselect_b32 s4, 0x40a00000, 2.0
; GFX9-NEXT: s_cselect_b32 s5, 1.0, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX942-LABEL: fsub_constant_sel_constants_v4f32:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX942-NEXT: s_mov_b32 s3, 0x41500000
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_bitcmp1_b32 s2, 0
; GFX942-NEXT: s_cselect_b32 s2, s3, 0x40c00000
; GFX942-NEXT: s_cselect_b32 s3, 0x41100000, 4.0
; GFX942-NEXT: s_cselect_b32 s4, 0x40a00000, 2.0
; GFX942-NEXT: s_cselect_b32 s5, 1.0, 0
; GFX942-NEXT: v_mov_b32_e32 v2, s5
; GFX942-NEXT: v_mov_b32_e32 v3, s4
; GFX942-NEXT: v_mov_b32_e32 v4, s3
; GFX942-NEXT: v_mov_b32_e32 v5, s2
; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1]
; GFX942-NEXT: s_endpgm
%sel = select i1 %cond, <4 x float> <float -2.0, float -3.0, float -4.0, float -5.0>, <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0>
%bo = fsub <4 x float> <float -1.0, float 2.0, float 5.0, float 8.0>, %sel
store <4 x float> %bo, ptr addrspace(1) %p, align 32
Expand Down
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