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[GlobalISel] Add G_ABS computeKnownBits #154413

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Merged
merged 14 commits into from
Sep 21, 2025
Merged

[GlobalISel] Add G_ABS computeKnownBits #154413

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519caea
[GlobalISel] Add G_ABS computeKnownBits
r41k0u Aug 19, 2025
237f996
[GlobalISel] Add more tests for G_ABS computeKnownBits
r41k0u Aug 31, 2025
6fe08a8
[GlobalISel] Add cache assertion and clearing to GISelValueTracking::…
r41k0u Sep 1, 2025
7898992
[GlobalISel] Add sign extension tests for knownbits_abs, update tests
r41k0u Sep 1, 2025
90c15e8
[GlobalISel] Fix formatting in GISelValueTrackingPrinterPass::run
r41k0u Sep 1, 2025
4973773
[GlobalIsel] Add computeNumSignBitsImpl to GISelValueTracking
r41k0u Sep 3, 2025
1a5237c
[GlobalISel] Update aarch64-smull.ll test
r41k0u Sep 3, 2025
b1fa17d
[GlobalISel] Replace relevant occurences of computeNumSignBits to com…
r41k0u Sep 4, 2025
6729b0f
[GlobalISel] Fix depth for calling computeKnownBitsImpl in computeNum…
r41k0u Sep 4, 2025
bcd8393
[GlobalISel] clang-format
r41k0u Sep 5, 2025
7e84ad1
[GlobalISel] Replace getKnownBits with its Impl in getValidShiftAmoun…
r41k0u Sep 7, 2025
a185946
[GlobalISel] Remove workarounds for cache assertion while adding G_AB…
r41k0u Sep 19, 2025
66cf46f
[GlobalISel] clang-format
r41k0u Sep 19, 2025
7e0073d
[GlobalISel] Update AMDGPU tests for G_ABS KnownBits tracking
r41k0u Sep 20, 2025
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8 changes: 8 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -675,6 +675,14 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
case TargetOpcode::G_ABS: {
Register SrcReg = MI.getOperand(1).getReg();
computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
Known = Known.abs();
Known.Zero.setHighBits(computeNumSignBits(SrcReg, DemandedElts, Depth + 1) -
1);
break;
}
}

LLVM_DEBUG(dumpResult(MI, Known, Depth));
Expand Down
83 changes: 83 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
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@@ -0,0 +1,83 @@
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -passes='print<gisel-value-tracking>' -filetype=null %s 2>&1 | FileCheck %s

---
name: Cst
body: |
bb.0:
; CHECK-LABEL: name: @Cst
; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:00010011 SignBits:3
%0:_(s8) = G_CONSTANT i8 19
%1:_(s8) = G_ABS %0
...
---
name: CstNeg
body: |
bb.0:
; CHECK-LABEL: name: @CstNeg
; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:00010010 SignBits:3
%0:_(s8) = G_CONSTANT i8 238
%1:_(s8) = G_ABS %0
...
---
name: SplatVecCst
body: |
bb.0:
; CHECK-LABEL: name: @SplatVecCst
; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:00000110 SignBits:5
%0:_(s8) = G_CONSTANT i8 250
%1:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %0(s8)
%2:_(<vscale x 16 x s8>) = G_ABS %1
...
---
name: VecCst
body: |
bb.0:
; CHECK-LABEL: name: @VecCst
; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3
; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3
; CHECK-NEXT: %3:_ KnownBits:00?????1 SignBits:2
%0:_(s8) = G_CONSTANT i8 25
%1:_(s8) = G_CONSTANT i8 225
%2:_(<2 x s8>) = G_BUILD_VECTOR %0:_(s8), %1:_(s8)
%3:_(<2 x s8>) = G_ABS %2
...
---
name: ImplicitDef
body: |
bb.0:
; CHECK-LABEL: name: @ImplicitDef
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
%0:_(s8) = G_IMPLICIT_DEF
%1:_(s8) = G_ABS %0
...
---
name: CstSext
body: |
bb.0:
; CHECK-LABEL: name: @CstSext
; CHECK-NEXT: %0:_ KnownBits:11000111 SignBits:2
; CHECK-NEXT: %1:_ KnownBits:1111111111000111 SignBits:10
; CHECK-NEXT: %2:_ KnownBits:0000000000111001 SignBits:10
%0:_(s8) = G_CONSTANT i8 199
%1:_(s16) = G_SEXT %0
%2:_(s16) = G_ABS %1
...
---
name: ImplicitDefSext
body: |
bb.0:
; CHECK-LABEL: name: @ImplicitDefSext
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8
%0:_(s8) = G_IMPLICIT_DEF
%1:_(s16) = G_SEXT %0
%2:_(s16) = G_ABS %1
...
20 changes: 6 additions & 14 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
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Expand Up @@ -302,11 +302,8 @@ body: |
; SI-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG]]
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI-NEXT: [[ABS1:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG1]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ABS1]], [[C1]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ABS1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ABS]], [[SHL]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
;
Expand Down Expand Up @@ -429,16 +426,11 @@ body: |
; SI-NEXT: [[ABS2:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG2]]
; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI-NEXT: [[ABS3:%[0-9]+]]:_(s32) = G_ABS [[SEXT_INREG3]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ABS]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ABS1]], [[C1]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ABS1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ABS]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ABS2]], [[C1]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ABS3]], [[C1]]
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ABS3]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ABS2]], [[SHL1]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
Expand Down
7 changes: 1 addition & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
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Expand Up @@ -459,8 +459,6 @@ define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
Expand Down Expand Up @@ -548,12 +546,9 @@ define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
; GFX8-NEXT: s_abs_i32 s2, s2
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: abs_sgpr_v3i16:
Expand Down
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