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[LLDB][AArch64] Make TPIDR a generic tp register #154444

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Merged
merged 7 commits into from
Sep 4, 2025
Merged

[LLDB][AArch64] Make TPIDR a generic tp register #154444

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3b6592c
Make tpidr a generic thread pointer register on aarch
Jlalond Aug 19, 2025
10faf5b
Add a test
Jlalond Aug 20, 2025
84f48ee
Format
Jlalond Aug 20, 2025
2fa8e36
Refactor defines
Jlalond Aug 21, 2025
1292a0d
Fix some weird formatting in the defines from gcf
Jlalond Aug 21, 2025
e1c02b8
Move the clang-format off to the top of the defines
Jlalond Aug 21, 2025
b7f8f3f
Implement feedback from David
Jlalond Aug 27, 2025
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11 changes: 10 additions & 1 deletion lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,16 @@ static lldb_private::RegisterInfo g_register_infos_mte[] = {
DEFINE_EXTENSION_REG(mte_ctrl)};

static lldb_private::RegisterInfo g_register_infos_tls[] = {
DEFINE_EXTENSION_REG(tpidr),
{"tpidr",
nullptr,
8,
0,
lldb::eEncodingUint,
lldb::eFormatHex,
{LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_REGNUM_GENERIC_TP},
nullptr,
nullptr,
nullptr},
// Only present when SME is present
DEFINE_EXTENSION_REG(tpidr2)};

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2 changes: 2 additions & 0 deletions lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,8 @@ def check_tls_reg(self, registers):
for register in registers:
self.expect("p {}_was_set".format(register), substrs=["true"])

self.expect("reg read tp", substrs=[hex(set_values["tpidr"])])

@skipUnlessArch("aarch64")
@skipUnlessPlatform(["linux"])
def test_tls_no_sme(self):
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