[RISCV] Use llvm_anyint_ty instead of llvm_any_ty for scalar intrinsics. NFC

[topperc]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-llvm-ir

Author: Craig Topper (topperc)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/154816.diff

2 Files Affected:

• (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+5-5)
• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+9)

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 243100f0c7180..c74cc3c04833a 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -80,11 +80,11 @@ let TargetPrefix = "riscv" in {
 let TargetPrefix = "riscv" in {
 
   class BitManipGPRIntrinsics
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable]>;
   class BitManipGPRGPRIntrinsics
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable]>;
 
@@ -115,11 +115,11 @@ let TargetPrefix = "riscv" in {
 
   // Zimop
   def int_riscv_mopr
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
   def int_riscv_moprr
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
 } // TargetPrefix = "riscv"
@@ -135,7 +135,7 @@ defvar NoScalarOperand = 0xF;
 defvar NoVLOperand = 0x1F;
 
 class RISCVVIntrinsic {
-  // These intrinsics may accept illegal integer values in their llvm_any_ty
+  // These intrinsics may accept illegal integer values in their llvm_anyint_ty
   // operand, so they have to be extended.
   Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
   bits<4> ScalarOperand = NoScalarOperand;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4a1db80076530..ff625a8bcda30 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1809,6 +1809,15 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::riscv_masked_atomicrmw_umax_i32:
   case Intrinsic::riscv_masked_atomicrmw_umin_i32:
   case Intrinsic::riscv_masked_cmpxchg_i32:
+  case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
+  case Intrinsic::riscv_masked_atomicrmw_add_i64:
+  case Intrinsic::riscv_masked_atomicrmw_sub_i64:
+  case Intrinsic::riscv_masked_atomicrmw_nand_i64:
+  case Intrinsic::riscv_masked_atomicrmw_max_i64:
+  case Intrinsic::riscv_masked_atomicrmw_min_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umax_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umin_i64:
+  case Intrinsic::riscv_masked_cmpxchg_i64:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::i32;
     Info.ptrVal = I.getArgOperand(0);

[lenary]

LGTM.

Looks like you stacked this, I'm only reviewing the changes to llvm/include/llvm/IR/IntrinsicsRISCV.td - I presume the atomic i64 changes are in another PR in my backlog.

[topperc]

LGTM.

Looks like you stacked this, I'm only reviewing the changes to llvm/include/llvm/IR/IntrinsicsRISCV.td - I presume the atomic i64 changes are in another PR in my backlog.

Oops. I'll unstack it.