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[AMDGPU][SPIRV] Use SPIR-V syncscopes for some AMDGCN BIs #154867

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Merged
merged 8 commits into from
Sep 29, 2025
Merged

[AMDGPU][SPIRV] Use SPIR-V syncscopes for some AMDGCN BIs #154867

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f65fa1d
Use "device" instead of "agent" and "subgroup" instead of "wavefront"…
AlexVlx Aug 22, 2025
4d6413c
Hoist scope mapping into named function.
AlexVlx Aug 22, 2025
577d516
Merge branch 'amdgcn_spirv_syncscopes' of https://github.com/AlexVlx/…
AlexVlx Aug 22, 2025
e744e4d
Fix test.
AlexVlx Aug 22, 2025
71bf5b3
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Aug 27, 2025
bfd0192
Merge branch 'main' into amdgcn_spirv_syncscopes
AlexVlx Sep 3, 2025
e76680e
Merge branches 'amdgcn_spirv_syncscopes' and 'amdgcn_spirv_syncscopes…
AlexVlx Sep 9, 2025
e15d1da
Merge branch 'main' into amdgcn_spirv_syncscopes
AlexVlx Sep 23, 2025
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27 changes: 23 additions & 4 deletions clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -192,9 +192,17 @@ static Value *emitFPIntBuiltin(CodeGenFunction &CGF,
return CGF.Builder.CreateCall(F, {Src0, Src1});
}

static inline StringRef mapScopeToSPIRV(StringRef AMDGCNScope) {
if (AMDGCNScope == "agent")
return "device";
if (AMDGCNScope == "wavefront")
return "subgroup";
return AMDGCNScope;
}

// For processing memory ordering and memory scope arguments of various
// amdgcn builtins.
// \p Order takes a C++11 comptabile memory-ordering specifier and converts
// \p Order takes a C++11 compatible memory-ordering specifier and converts
// it into LLVM's memory ordering specifier using atomic C ABI, and writes
// to \p AO. \p Scope takes a const char * and converts it into AMDGCN
// specific SyncScopeID and writes it to \p SSID.
Expand Down Expand Up @@ -227,6 +235,8 @@ void CodeGenFunction::ProcessOrderScopeAMDGCN(Value *Order, Value *Scope,
// Some of the atomic builtins take the scope as a string name.
StringRef scp;
if (llvm::getConstantStringInfo(Scope, scp)) {
if (getTarget().getTriple().isSPIRV())
scp = mapScopeToSPIRV(scp);
SSID = getLLVMContext().getOrInsertSyncScopeID(scp);
return;
}
Expand All @@ -238,13 +248,19 @@ void CodeGenFunction::ProcessOrderScopeAMDGCN(Value *Order, Value *Scope,
SSID = llvm::SyncScope::System;
break;
case 1: // __MEMORY_SCOPE_DEVICE
SSID = getLLVMContext().getOrInsertSyncScopeID("agent");
if (getTarget().getTriple().isSPIRV())
SSID = getLLVMContext().getOrInsertSyncScopeID("device");
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@yxsamliu yxsamliu Sep 11, 2025

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Will they be translate back to agent when we convert SPIRV to bitcode for amdgcn?

Do we have lit tests to cover that?

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@AlexVlx AlexVlx Sep 17, 2025

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Yes, reverse translation maps from SPIR-V to AMDGPU; we don't test this in LLVM yet because we don't use the BE, yet, reverse translation is done in the OOT translator.

else
SSID = getLLVMContext().getOrInsertSyncScopeID("agent");
break;
case 2: // __MEMORY_SCOPE_WRKGRP
SSID = getLLVMContext().getOrInsertSyncScopeID("workgroup");
break;
case 3: // __MEMORY_SCOPE_WVFRNT
SSID = getLLVMContext().getOrInsertSyncScopeID("wavefront");
if (getTarget().getTriple().isSPIRV())
SSID = getLLVMContext().getOrInsertSyncScopeID("subgroup");
else
SSID = getLLVMContext().getOrInsertSyncScopeID("wavefront");
break;
case 4: // __MEMORY_SCOPE_SINGLE
SSID = llvm::SyncScope::SingleThread;
Expand Down Expand Up @@ -1452,7 +1468,10 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
//
// The global/flat cases need to use agent scope to consistently produce
// the native instruction instead of a cmpxchg expansion.
SSID = getLLVMContext().getOrInsertSyncScopeID("agent");
if (getTarget().getTriple().isSPIRV())
SSID = getLLVMContext().getOrInsertSyncScopeID("device");
else
SSID = getLLVMContext().getOrInsertSyncScopeID("agent");
AO = AtomicOrdering::Monotonic;

// The v2bf16 builtin uses i16 instead of a natural bfloat type.
Expand Down
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