Skip to content

[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence #154952

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Sep 3, 2025
Merged

[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence #154952

Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
01480d7
update one with reg_sequence
broxigarchen Aug 22, 2025
799ff37
use v_mov_b32
broxigarchen Sep 2, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 1 addition & 3 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3106,9 +3106,7 @@ def : GCNPat<

def : GCNPat<
(i64 (DivergentUnaryFrag<zext> i16:$src)),
(REG_SEQUENCE VReg_64,
(INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0,
(S_MOV_B32 (i32 0)), sub1)
(REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (S_MOV_B32 (i32 0)), sub1)
>;

def : GCNPat<
Expand Down