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[NFC][MC][Lanai] Rearrange decoder functions for Lanai disassembler #154993

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Merged
jurahul merged 1 commit into from
Aug 25, 2025
+80 −106
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[NFC][MC][Lanai] Rearrange decoder functions for Lanai disassembler #154993

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186 changes: 80 additions & 106 deletions llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -47,34 +47,100 @@ LLVMInitializeLanaiDisassembler() {
LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
: MCDisassembler(STI, Ctx) {}

// Forward declare because the autogenerated code will reference this.
// Definition is further down.
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
// clang-format off
static const unsigned GPRDecoderTable[] = {
Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
Lanai::R30, Lanai::R31
};
// clang-format on

DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const MCDisassembler * /*Decoder*/) {
if (RegNo > 31)
return MCDisassembler::Fail;

unsigned Reg = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder);
const MCDisassembler *Decoder) {
// RI memory values encoded using 23 bits:
// 5 bit register, 16 bit constant
unsigned Register = (Insn >> 18) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
unsigned Offset = (Insn & 0xffff);
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));

return MCDisassembler::Success;
}

static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder);
const MCDisassembler *Decoder) {
// RR memory values encoded using 20 bits:
// 5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
unsigned Register = (Insn >> 15) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
Register = (Insn >> 10) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));

return MCDisassembler::Success;
}

static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder);
const MCDisassembler *Decoder) {
// RI memory values encoded using 17 bits:
// 5 bit register, 10 bit constant
unsigned Register = (Insn >> 12) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
unsigned Offset = (Insn & 0x3ff);
Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));

static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder);
return MCDisassembler::Success;
}

static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder);
static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
uint64_t Address, uint64_t Offset,
uint64_t Width, MCInst &MI,
const MCDisassembler *Decoder) {
return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
Width, /*InstSize=*/0);
}

static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
Decoder))
MI.addOperand(MCOperand::createImm(Insn));
return MCDisassembler::Success;
}

static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder);
const MCDisassembler *Decoder) {
unsigned Offset = (Insn & 0xffff);
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));

return MCDisassembler::Success;
}

static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
if (Val >= LPCC::UNKNOWN)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}

#include "LanaiGenDisassemblerTables.inc"

Expand Down Expand Up @@ -157,95 +223,3 @@ LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,

return MCDisassembler::Fail;
}

static const unsigned GPRDecoderTable[] = {
Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
Lanai::R30, Lanai::R31};

DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const MCDisassembler * /*Decoder*/) {
if (RegNo > 31)
return MCDisassembler::Fail;

unsigned Reg = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
// RI memory values encoded using 23 bits:
// 5 bit register, 16 bit constant
unsigned Register = (Insn >> 18) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
unsigned Offset = (Insn & 0xffff);
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));

return MCDisassembler::Success;
}

static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
// RR memory values encoded using 20 bits:
// 5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
unsigned Register = (Insn >> 15) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
Register = (Insn >> 10) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));

return MCDisassembler::Success;
}

static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
// RI memory values encoded using 17 bits:
// 5 bit register, 10 bit constant
unsigned Register = (Insn >> 12) & 0x1f;
Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
unsigned Offset = (Insn & 0x3ff);
Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));

return MCDisassembler::Success;
}

static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
uint64_t Address, uint64_t Offset,
uint64_t Width, MCInst &MI,
const MCDisassembler *Decoder) {
return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
Width, /*InstSize=*/0);
}

static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
Decoder))
MI.addOperand(MCOperand::createImm(Insn));
return MCDisassembler::Success;
}

static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
unsigned Offset = (Insn & 0xffff);
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));

return MCDisassembler::Success;
}

static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
if (Val >= LPCC::UNKNOWN)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}