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[GISel][AArch64] Create emitCMP instead of cloning a virtual register (NFC) #155262

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Merged
merged 2 commits into from
Nov 13, 2025
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[GISel][AArch64] Create emitCMP instead of cloning a virtual register (NFC) #155262

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[GISel][AArch64] Create emitCMP instead of cloning a virtual register…
AZero13 Aug 25, 2025
e054677
Remove brackets
AZero13 Nov 7, 2025
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17 changes: 13 additions & 4 deletions llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -310,6 +310,8 @@ class AArch64InstructionSelector : public InstructionSelector {
MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitSBCS(Register Dst, MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitCMP(MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitTST(MachineOperand &LHS, MachineOperand &RHS,
Expand Down Expand Up @@ -4414,6 +4416,15 @@ AArch64InstructionSelector::emitSBCS(Register Dst, MachineOperand &LHS,
return emitInstr(OpcTable[Is32Bit], {Dst}, {LHS, RHS}, MIRBuilder);
}

MachineInstr *
AArch64InstructionSelector::emitCMP(MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const {
MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;
return emitSUBS(MRI.createVirtualRegister(RC), LHS, RHS, MIRBuilder);
}

MachineInstr *
AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const {
Expand Down Expand Up @@ -4466,8 +4477,7 @@ MachineInstr *AArch64InstructionSelector::emitIntegerCompare(
// Fold the compare into a cmn or tst if possible.
if (auto FoldCmp = tryFoldIntegerCompare(LHS, RHS, Predicate, MIRBuilder))
return FoldCmp;
auto Dst = MRI.cloneVirtualRegister(LHS.getReg());
return emitSUBS(Dst, LHS, RHS, MIRBuilder);
return emitCMP(LHS, RHS, MIRBuilder);
}

MachineInstr *AArch64InstructionSelector::emitCSetForFCmp(
Expand Down Expand Up @@ -4872,9 +4882,8 @@ MachineInstr *AArch64InstructionSelector::emitConjunctionRec(

// Produce a normal comparison if we are first in the chain
if (!CCOp) {
auto Dst = MRI.cloneVirtualRegister(LHS);
if (isa<GICmp>(Cmp))
return emitSUBS(Dst, Cmp->getOperand(2), Cmp->getOperand(3), MIB);
return emitCMP(Cmp->getOperand(2), Cmp->getOperand(3), MIB);
return emitFPCompare(Cmp->getOperand(2).getReg(),
Cmp->getOperand(3).getReg(), MIB);
}
Expand Down
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