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[RISCV] Account for ADDI immediate range in select of two constants w/ zicond #155471

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Merged
preames merged 4 commits into from
Aug 27, 2025
Merged

[RISCV] Account for ADDI immediate range in select of two constants w/ zicond #155471

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93bfcbb
[RISCV] Account for ADDI immediate range in select of two constants w…
preames Aug 26, 2025
6bc72be
Move the fudge factor to a future pr
preames Aug 26, 2025
ca8c795
Address review comment
preames Aug 26, 2025
1f80291
one more typo fix
preames Aug 26, 2025
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17 changes: 12 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9280,11 +9280,18 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
}

const int TrueValCost = RISCVMatInt::getIntMatCost(
TrueVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
const int FalseValCost = RISCVMatInt::getIntMatCost(
FalseVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
bool IsCZERO_NEZ = TrueValCost <= FalseValCost;
auto getCost = [&](const APInt &Delta, const APInt &Addend) {
const int DeltaCost = RISCVMatInt::getIntMatCost(
Delta, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
// Does the addend fold into an ADDI
if (Addend.isSignedIntN(12))
return DeltaCost;
const int AddendCost = RISCVMatInt::getIntMatCost(
Addend, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
return AddendCost + DeltaCost;
};
bool IsCZERO_NEZ = getCost(FalseVal - TrueVal, TrueVal) <=
getCost(TrueVal - FalseVal, FalseVal);
SDValue LHSVal = DAG.getConstant(
IsCZERO_NEZ ? FalseVal - TrueVal : TrueVal - FalseVal, DL, VT);
SDValue RHSVal =
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14 changes: 6 additions & 8 deletions llvm/test/CodeGen/RISCV/select-const.ll
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Expand Up @@ -506,11 +506,10 @@ define i32 @select_nonnegative_lui_addi(i32 signext %x) {
; RV32ZICOND-LABEL: select_nonnegative_lui_addi:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 1048572
; RV32ZICOND-NEXT: addi a1, a1, 25
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: lui a1, 4
; RV32ZICOND-NEXT: add a0, a0, a1
; RV32ZICOND-NEXT: addi a1, a1, -25
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
; RV64I-LABEL: select_nonnegative_lui_addi:
Expand All @@ -536,11 +535,10 @@ define i32 @select_nonnegative_lui_addi(i32 signext %x) {
; RV64ZICOND-LABEL: select_nonnegative_lui_addi:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 1048572
; RV64ZICOND-NEXT: addi a1, a1, 25
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
; RV64ZICOND-NEXT: lui a1, 4
; RV64ZICOND-NEXT: add a0, a0, a1
; RV64ZICOND-NEXT: addi a1, a1, -25
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: addi a0, a0, 25
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 16384, i32 25
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