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AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check #155603

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Merged
merged 2 commits into from
Sep 2, 2025
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AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check #155603

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07fefca
AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check
arsenm Aug 27, 2025
ec7dbe2
merge exec check
arsenm Aug 28, 2025
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58 changes: 34 additions & 24 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4758,30 +4758,41 @@ MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
return Inst32;
}

bool SIInstrInfo::physRegUsesConstantBus(const MachineOperand &RegOp) const {
// Null is free
Register Reg = RegOp.getReg();
if (Reg == AMDGPU::SGPR_NULL || Reg == AMDGPU::SGPR_NULL64)
return false;

// SGPRs use the constant bus

// FIXME: implicit registers that are not part of the MCInstrDesc's implicit
// physical register operands should also count, except for exec.
if (RegOp.isImplicit())
return Reg == AMDGPU::VCC || Reg == AMDGPU::VCC_LO || Reg == AMDGPU::M0;

// SGPRs use the constant bus
return AMDGPU::SReg_32RegClass.contains(Reg) ||
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isSGPRPhysReg()? Just in case we will have more classes, or got ttmp or something like that in the future.

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Separate change, this just shuffles the existing logic

AMDGPU::SReg_64RegClass.contains(Reg);
}

bool SIInstrInfo::regUsesConstantBus(const MachineOperand &RegOp,
const MachineRegisterInfo &MRI) const {
Register Reg = RegOp.getReg();
return Reg.isVirtual() ? RI.isSGPRClass(MRI.getRegClass(Reg))
: physRegUsesConstantBus(RegOp);
}

bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
const MachineOperand &MO,
const MCOperandInfo &OpInfo) const {
// Literal constants use the constant bus.
if (!MO.isReg())
return !isInlineConstant(MO, OpInfo);

if (!MO.isUse())
return false;

if (MO.getReg().isVirtual())
return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));

// Null is free
if (MO.getReg() == AMDGPU::SGPR_NULL || MO.getReg() == AMDGPU::SGPR_NULL64)
return false;

// SGPRs use the constant bus
if (MO.isImplicit()) {
return MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
MO.getReg() == AMDGPU::VCC_LO;
}
return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
AMDGPU::SReg_64RegClass.contains(MO.getReg());
Register Reg = MO.getReg();
return Reg.isVirtual() ? RI.isSGPRClass(MRI.getRegClass(Reg))
: physRegUsesConstantBus(MO);
}

static Register findImplicitSGPRRead(const MachineInstr &MI) {
Expand Down Expand Up @@ -6250,13 +6261,12 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
continue;
const MachineOperand &Op = MI.getOperand(i);
if (Op.isReg()) {
RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
if (!SGPRsUsed.count(SGPR) &&
// FIXME: This can access off the end of the operands() array.
usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {
if (--ConstantBusLimit <= 0)
return false;
SGPRsUsed.insert(SGPR);
if (Op.isUse()) {
RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
if (regUsesConstantBus(Op, MRI) && SGPRsUsed.insert(SGPR).second) {
if (--ConstantBusLimit <= 0)
return false;
}
}
} else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
!isInlineConstant(Op, InstDesc.operands()[i])) {
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1195,6 +1195,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// This function will return false if you pass it a 32-bit instruction.
bool hasVALU32BitEncoding(unsigned Opcode) const;

bool physRegUsesConstantBus(const MachineOperand &Reg) const;
bool regUsesConstantBus(const MachineOperand &Reg,
const MachineRegisterInfo &MRI) const;

/// Returns true if this operand uses the constant bus.
bool usesConstantBus(const MachineRegisterInfo &MRI,
const MachineOperand &MO,
Expand Down
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