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[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD #155972

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Merged
merged 3 commits into from
Sep 3, 2025
Merged

[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD #155972

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e353db9
[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD
Aug 29, 2025
0cd1c04
Replace getFirst3RegLLTs with getFirst3Reg
Aug 29, 2025
e466f25
Fix virtual register numbering
Aug 29, 2025
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9 changes: 9 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4773,6 +4773,15 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerVectorReduction(MI);
case G_VAARG:
return lowerVAArg(MI);
case G_ATOMICRMW_SUB: {
auto [Ret, RetLLT, Mem, MemLLT, Val, ValLLT] = MI.getFirst3RegLLTs();
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@arsenm arsenm Aug 29, 2025

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All of the types involved are the same, so just use getFIrst3Reg?

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@ReVe1uv ReVe1uv Aug 29, 2025

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Yes, after reusing the Ret register to avoid creating a new copy instruction, should just use getFirst3Reg.

MachineMemOperand *MMO = *MI.memoperands_begin();

auto VNeg = MIRBuilder.buildNeg(ValLLT, Val);
MIRBuilder.buildAtomicRMW(G_ATOMICRMW_ADD, Ret, Mem, VNeg, *MMO);
MI.eraseFromParent();
return Legalized;
}
}
}

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6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -700,6 +700,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
.clampScalar(0, sXLen, sXLen);

getActionDefinitionsBuilder(G_ATOMICRMW_SUB)
.libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
.clampScalar(0, sXLen, sXLen)
.lower();

getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
}
Expand Down Expand Up @@ -738,6 +743,7 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return true;
}
case Intrinsic::riscv_masked_atomicrmw_add:
case Intrinsic::riscv_masked_atomicrmw_sub:
return true;
}
}
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