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[MachineLICM] Fine tune getRegPressureSetLimit #156173

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4 changes: 3 additions & 1 deletion llvm/lib/CodeGen/MachineLICM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -396,13 +396,15 @@ bool MachineLICMImpl::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");

if (PreRegAlloc) {
RegisterClassInfo RegClassInfo;
RegClassInfo.runOnMachineFunction(MF);
// Estimate register pressure during pre-regalloc pass.
unsigned NumRPS = TRI->getNumRegPressureSets();
RegPressure.resize(NumRPS);
llvm::fill(RegPressure, 0);
RegLimit.resize(NumRPS);
for (unsigned i = 0, e = NumRPS; i != e; ++i)
RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
RegLimit[i] = RegClassInfo.getRegPressureSetLimit(i);
}

if (HoistConstLoads)
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670 changes: 345 additions & 325 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
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670 changes: 345 additions & 325 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
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218 changes: 107 additions & 111 deletions llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
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104 changes: 52 additions & 52 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11089,27 +11089,27 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX7LESS-NEXT: s_mov_b64 s[8:9], 0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_lshl_b32 s6, s6, 16
; GFX7LESS-NEXT: s_lshl_b32 s11, s6, 16
; GFX7LESS-NEXT: s_and_b32 s4, s2, -4
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: s_load_dword s3, s[4:5], 0x0
; GFX7LESS-NEXT: s_and_b32 s2, s2, 3
; GFX7LESS-NEXT: s_lshl_b32 s10, s2, 3
; GFX7LESS-NEXT: s_load_dword s3, s[4:5], 0x0
; GFX7LESS-NEXT: v_mul_f32_e64 v0, 1.0, s6
; GFX7LESS-NEXT: s_lshl_b32 s2, 0xffff, s10
; GFX7LESS-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX7LESS-NEXT: s_not_b32 s2, s2
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s3
; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX7LESS-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v0, s10, v1
; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_mul_f32_e64 v2, 1.0, s11
; GFX7LESS-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7LESS-NEXT: v_add_f32_e32 v0, v0, v4
; GFX7LESS-NEXT: v_add_f32_e32 v0, v0, v2
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v0, s10, v0
; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_and_b32_e32 v2, s2, v1
; GFX7LESS-NEXT: v_or_b32_e32 v0, v2, v0
; GFX7LESS-NEXT: v_mov_b32_e32 v3, v1
Expand Down Expand Up @@ -11774,26 +11774,26 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
define amdgpu_kernel void @uniform_fadd_v2f16(ptr addrspace(1) %result, ptr addrspace(1) %uniform.ptr, <2 x half> %val) {
; GFX7LESS-LABEL: uniform_fadd_v2f16:
; GFX7LESS: ; %bb.0:
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
; GFX7LESS-NEXT: s_mov_b64 s[8:9], 0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_lshr_b32 s4, s6, 16
; GFX7LESS-NEXT: s_mov_b32 s4, s2
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: s_lshr_b32 s2, s6, 16
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v0, s6
; GFX7LESS-NEXT: s_load_dword s5, s[2:3], 0x0
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v1, s4
; GFX7LESS-NEXT: s_load_dword s3, s[4:5], 0x0
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v1, s2
; GFX7LESS-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7LESS-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v2, s5
; GFX7LESS-NEXT: s_lshr_b32 s4, s5, 16
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v3, s4
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v2, s3
; GFX7LESS-NEXT: s_lshr_b32 s2, s3, 16
; GFX7LESS-NEXT: v_cvt_f32_f16_e32 v3, s2
; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: s_mov_b32 s4, s2
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX7LESS-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7LESS-NEXT: v_cvt_f16_f32_e32 v3, v3
Expand Down Expand Up @@ -12070,56 +12070,56 @@ define amdgpu_kernel void @uniform_fadd_v2f16(ptr addrspace(1) %result, ptr addr
define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr addrspace(1) %uniform.ptr, <2 x bfloat> %val) {
; GFX7LESS-LABEL: uniform_fadd_v2bf16:
; GFX7LESS: ; %bb.0:
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7LESS-NEXT: s_mov_b64 s[8:9], 0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_and_b32 s4, s6, 0xffff0000
; GFX7LESS-NEXT: s_lshl_b32 s5, s6, 16
; GFX7LESS-NEXT: s_load_dword s6, s[2:3], 0x0
; GFX7LESS-NEXT: v_mul_f32_e64 v0, 1.0, s5
; GFX7LESS-NEXT: v_mul_f32_e64 v1, 1.0, s4
; GFX7LESS-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_and_b32 s4, s6, 0xffff0000
; GFX7LESS-NEXT: s_lshl_b32 s5, s6, 16
; GFX7LESS-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX7LESS-NEXT: v_mov_b32_e32 v3, s5
; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4
; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: s_mov_b32 s4, s2
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: s_load_dword s9, s[4:5], 0x0
; GFX7LESS-NEXT: s_mov_b64 s[2:3], 0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_and_b32 s8, s6, 0xffff0000
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_and_b32 s10, s9, 0xffff0000
; GFX7LESS-NEXT: s_lshl_b32 s11, s9, 16
; GFX7LESS-NEXT: s_lshl_b32 s9, s6, 16
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s11
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s10
; GFX7LESS-NEXT: s_mov_b32 s6, -1
; GFX7LESS-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX7LESS-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7LESS-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX7LESS-NEXT: v_mul_f32_e32 v2, 1.0, v2
; GFX7LESS-NEXT: s_waitcnt expcnt(0)
; GFX7LESS-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX7LESS-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX7LESS-NEXT: v_add_f32_e32 v4, v4, v0
; GFX7LESS-NEXT: v_add_f32_e32 v5, v5, v1
; GFX7LESS-NEXT: v_alignbit_b32 v3, v2, v3, 16
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v2, 16, v5
; GFX7LESS-NEXT: v_alignbit_b32 v2, v2, v4, 16
; GFX7LESS-NEXT: v_mov_b32_e32 v5, v3
; GFX7LESS-NEXT: v_mov_b32_e32 v4, v2
; GFX7LESS-NEXT: buffer_atomic_cmpswap v[4:5], off, s[4:7], 0 glc
; GFX7LESS-NEXT: v_mul_f32_e64 v2, 1.0, s9
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Most of these tests changes look like it's now not hoisting out of a loop in cases that shouldn't be pressure constrained

; GFX7LESS-NEXT: v_mul_f32_e32 v1, 1.0, v1
; GFX7LESS-NEXT: v_mul_f32_e64 v3, 1.0, s8
; GFX7LESS-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7LESS-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX7LESS-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX7LESS-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX7LESS-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7LESS-NEXT: v_add_f32_e32 v2, v4, v2
; GFX7LESS-NEXT: v_add_f32_e32 v3, v5, v3
; GFX7LESS-NEXT: v_alignbit_b32 v1, v0, v1, 16
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v0, 16, v3
; GFX7LESS-NEXT: v_alignbit_b32 v0, v0, v2, 16
; GFX7LESS-NEXT: v_mov_b32_e32 v3, v1
; GFX7LESS-NEXT: v_mov_b32_e32 v2, v0
; GFX7LESS-NEXT: buffer_atomic_cmpswap v[2:3], off, s[4:7], 0 glc
; GFX7LESS-NEXT: s_waitcnt vmcnt(0)
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
; GFX7LESS-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
; GFX7LESS-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX7LESS-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX7LESS-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
; GFX7LESS-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX7LESS-NEXT: s_andn2_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_cbranch_execnz .LBB21_1
; GFX7LESS-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s2, -1
; GFX7LESS-NEXT: v_mul_f32_e32 v0, 1.0, v2
; GFX7LESS-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7LESS-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7LESS-NEXT: v_mul_f32_e32 v1, 1.0, v3
; GFX7LESS-NEXT: v_mul_f32_e32 v1, 1.0, v1
; GFX7LESS-NEXT: v_alignbit_b32 v0, v0, v1, 16
; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7LESS-NEXT: s_endpgm
Expand Down
23 changes: 11 additions & 12 deletions llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
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Expand Up @@ -10,9 +10,7 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v0, s[0:1] offset:4
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, -4
Expand All @@ -21,7 +19,7 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: s_load_b32 s3, s[0:1], 0x0
; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, 0xffff, s2
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s3
Expand All @@ -35,18 +33,19 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, v1, s3, v0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v0, v4, v[0:1], s[0:1] glc
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
; GFX11-TRUE16-NEXT: buffer_gl0_inv
Expand Down
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