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[AMDGPU] Allow forming overflow op and folding abd to usubo if it is legal #156266

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[AMDGPU] Allow forming overflow op and folding abd to usubo if it is legal #156266

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4 changes: 4 additions & 0 deletions llvm/include/llvm/CodeGen/TargetLowering.h
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Expand Up @@ -3455,6 +3455,10 @@ class LLVM_ABI TargetLoweringBase {
/// matching of other patterns.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const {
// Form it if it is legal.
if (isOperationLegal(Opcode, VT))
return true;

// TODO: The default logic is inherited from code in CodeGenPrepare.
// The opcode should not make a difference by default?
if (Opcode != ISD::UADDO)
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -9788,7 +9788,8 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
// flag if the (scalar) type is illegal as this is more likely to legalize
// cleanly:
// abdu(lhs, rhs) -> sub(xor(sub(lhs, rhs), uof(lhs, rhs)), uof(lhs, rhs))
if (!IsSigned && VT.isScalarInteger() && !isTypeLegal(VT)) {
if (!IsSigned && (isOperationLegal(ISD::USUBO, VT) ||
(VT.isScalarInteger() && !isTypeLegal(VT)))) {
SDValue USubO =
DAG.getNode(ISD::USUBO, dl, DAG.getVTList(VT, MVT::i1), {LHS, RHS});
SDValue Cmp = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, USubO.getValue(1));
Expand Down
35 changes: 13 additions & 22 deletions llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
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Expand Up @@ -98,14 +98,12 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_i32 s0, s2, s2
; GFX7-NEXT: s_cmp_lt_u32 s0, s2
; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX7-NEXT: v_add_i32_e64 v0, s[0:1], s2, s2
; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_addc_u32 s0, s2, 0
; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
; GFX7-NEXT: ; %bb.1: ; %bb0
; GFX7-NEXT: v_mov_b32_e32 v0, 0
Expand All @@ -125,13 +123,11 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_i32 s0, s2, s2
; GFX9-NEXT: s_cmp_lt_u32 s0, s2
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[0:1], s2, s2
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: s_addc_u32 s0, s2, 0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
Expand All @@ -151,13 +147,11 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_i32 s1, s0, s0
; GFX10-NEXT: s_cmp_lt_u32 s1, s0
; GFX10-NEXT: s_cselect_b32 s1, -1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v0, s1, s0, s0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_addc_u32 s0, s0, 0
; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
; GFX10-NEXT: s_cselect_b32 s0, -1, 0
; GFX10-NEXT: s_andn2_b32 vcc_lo, exec_lo, s0
; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
Expand All @@ -177,15 +171,12 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_add_i32 s1, s0, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_lt_u32 s1, s0
; GFX11-NEXT: s_cselect_b32 s1, -1, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX11-NEXT: v_add_co_u32 v0, s1, s0, s0
; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_addc_u32 s0, s0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-NEXT: s_cbranch_vccnz .LBB1_2
; GFX11-NEXT: ; %bb.1: ; %bb0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
Expand Down
72 changes: 24 additions & 48 deletions llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
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Expand Up @@ -8946,8 +8946,7 @@ define void @flat_atomic_udec_wrap_i32_noret(ptr %ptr, i32 %in) {
; GCN1-NEXT: .LBB141_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_add_i32_e32 v3, vcc, -1, v4
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN1-NEXT: v_subrev_i32_e32 v3, vcc, 1, v4
; GCN1-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN1-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -8971,8 +8970,7 @@ define void @flat_atomic_udec_wrap_i32_noret(ptr %ptr, i32 %in) {
; GCN2-NEXT: .LBB141_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_add_u32_e32 v3, vcc, -1, v4
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN2-NEXT: v_subrev_u32_e32 v3, vcc, 1, v4
; GCN2-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN2-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -8996,9 +8994,8 @@ define void @flat_atomic_udec_wrap_i32_noret(ptr %ptr, i32 %in) {
; GCN3-NEXT: .LBB141_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN3-NEXT: v_subrev_co_u32_e32 v3, vcc, 1, v4
; GCN3-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN3-NEXT: v_add_u32_e32 v3, -1, v4
; GCN3-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
Expand Down Expand Up @@ -9027,8 +9024,7 @@ define void @flat_atomic_udec_wrap_i32_noret_offset(ptr %out, i32 %in) {
; GCN1-NEXT: .LBB142_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_add_i32_e32 v3, vcc, -1, v4
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN1-NEXT: v_subrev_i32_e32 v3, vcc, 1, v4
; GCN1-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN1-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -9054,8 +9050,7 @@ define void @flat_atomic_udec_wrap_i32_noret_offset(ptr %out, i32 %in) {
; GCN2-NEXT: .LBB142_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_add_u32_e32 v3, vcc, -1, v4
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN2-NEXT: v_subrev_u32_e32 v3, vcc, 1, v4
; GCN2-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN2-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -9079,9 +9074,8 @@ define void @flat_atomic_udec_wrap_i32_noret_offset(ptr %out, i32 %in) {
; GCN3-NEXT: .LBB142_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN3-NEXT: v_subrev_co_u32_e32 v3, vcc, 1, v4
; GCN3-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN3-NEXT: v_add_u32_e32 v3, -1, v4
; GCN3-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] offset:16 glc
Expand Down Expand Up @@ -9110,8 +9104,7 @@ define i32 @flat_atomic_udec_wrap_i32_ret(ptr %ptr, i32 %in) {
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v4, v3
; GCN1-NEXT: v_add_i32_e32 v3, vcc, -1, v4
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN1-NEXT: v_subrev_i32_e32 v3, vcc, 1, v4
; GCN1-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN1-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -9136,8 +9129,7 @@ define i32 @flat_atomic_udec_wrap_i32_ret(ptr %ptr, i32 %in) {
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v4, v3
; GCN2-NEXT: v_add_u32_e32 v3, vcc, -1, v4
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN2-NEXT: v_subrev_u32_e32 v3, vcc, 1, v4
; GCN2-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN2-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
Expand All @@ -9162,9 +9154,8 @@ define i32 @flat_atomic_udec_wrap_i32_ret(ptr %ptr, i32 %in) {
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v4, v3
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN3-NEXT: v_subrev_co_u32_e32 v3, vcc, 1, v4
; GCN3-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN3-NEXT: v_add_u32_e32 v3, -1, v4
; GCN3-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
Expand Down Expand Up @@ -9194,8 +9185,7 @@ define i32 @flat_atomic_udec_wrap_i32_ret_offset(ptr %out, i32 %in) {
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v1, v0
; GCN1-NEXT: v_add_i32_e32 v0, vcc, -1, v1
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN1-NEXT: v_subrev_i32_e32 v0, vcc, 1, v1
; GCN1-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v2
; GCN1-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
Expand All @@ -9221,8 +9211,7 @@ define i32 @flat_atomic_udec_wrap_i32_ret_offset(ptr %out, i32 %in) {
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v1, v0
; GCN2-NEXT: v_add_u32_e32 v0, vcc, -1, v1
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN2-NEXT: v_subrev_u32_e32 v0, vcc, 1, v1
; GCN2-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v2
; GCN2-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
Expand All @@ -9246,9 +9235,8 @@ define i32 @flat_atomic_udec_wrap_i32_ret_offset(ptr %out, i32 %in) {
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v4, v3
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GCN3-NEXT: v_subrev_co_u32_e32 v3, vcc, 1, v4
; GCN3-NEXT: v_cmp_gt_u32_e64 s[4:5], v4, v2
; GCN3-NEXT: v_add_u32_e32 v3, -1, v4
; GCN3-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] offset:16 glc
Expand Down Expand Up @@ -9279,8 +9267,7 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN1-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_add_i32_e32 v2, vcc, -1, v3
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN1-NEXT: v_subrev_i32_e32 v2, vcc, 1, v3
; GCN1-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN1-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
Expand All @@ -9307,8 +9294,7 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN2-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_add_u32_e32 v2, vcc, -1, v3
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN2-NEXT: v_subrev_u32_e32 v2, vcc, 1, v3
; GCN2-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN2-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
Expand All @@ -9335,9 +9321,8 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN3-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN3-NEXT: v_subrev_co_u32_e32 v2, vcc, 1, v3
; GCN3-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN3-NEXT: v_add_u32_e32 v2, -1, v3
; GCN3-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN3-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
Expand Down Expand Up @@ -9369,8 +9354,7 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_offset_scalar(ptr inreg
; GCN1-NEXT: .LBB146_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_add_i32_e32 v2, vcc, -1, v3
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN1-NEXT: v_subrev_i32_e32 v2, vcc, 1, v3
; GCN1-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN1-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
Expand Down Expand Up @@ -9399,8 +9383,7 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_offset_scalar(ptr inreg
; GCN2-NEXT: .LBB146_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_add_u32_e32 v2, vcc, -1, v3
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN2-NEXT: v_subrev_u32_e32 v2, vcc, 1, v3
; GCN2-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN2-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
Expand All @@ -9427,9 +9410,8 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_offset_scalar(ptr inreg
; GCN3-NEXT: .LBB146_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN3-NEXT: v_subrev_co_u32_e32 v2, vcc, 1, v3
; GCN3-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v3
; GCN3-NEXT: v_add_u32_e32 v2, -1, v3
; GCN3-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN3-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:16 glc
Expand Down Expand Up @@ -9463,8 +9445,7 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v5, v0
; GCN1-NEXT: v_add_i32_e32 v0, vcc, -1, v5
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN1-NEXT: v_subrev_i32_e32 v0, vcc, 1, v5
; GCN1-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN1-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN1-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
Expand Down Expand Up @@ -9493,8 +9474,7 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v5, v0
; GCN2-NEXT: v_add_u32_e32 v0, vcc, -1, v5
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN2-NEXT: v_subrev_u32_e32 v0, vcc, 1, v5
; GCN2-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN2-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN2-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
Expand Down Expand Up @@ -9523,9 +9503,8 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v5, v0
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN3-NEXT: v_subrev_co_u32_e32 v0, vcc, 1, v5
; GCN3-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN3-NEXT: v_add_u32_e32 v0, -1, v5
; GCN3-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
; GCN3-NEXT: flat_atomic_cmpswap v0, v[1:2], v[4:5] glc
Expand Down Expand Up @@ -9557,8 +9536,7 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_offset_scalar(ptr inreg %ou
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v5, v0
; GCN1-NEXT: v_add_i32_e32 v0, vcc, -1, v5
; GCN1-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN1-NEXT: v_subrev_i32_e32 v0, vcc, 1, v5
; GCN1-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN1-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN1-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
Expand Down Expand Up @@ -9587,8 +9565,7 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_offset_scalar(ptr inreg %ou
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v5, v0
; GCN2-NEXT: v_add_u32_e32 v0, vcc, -1, v5
; GCN2-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN2-NEXT: v_subrev_u32_e32 v0, vcc, 1, v5
; GCN2-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN2-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN2-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
Expand Down Expand Up @@ -9617,9 +9594,8 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_offset_scalar(ptr inreg %ou
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v5, v0
; GCN3-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN3-NEXT: v_subrev_co_u32_e32 v0, vcc, 1, v5
; GCN3-NEXT: v_cmp_lt_u32_e64 s[34:35], s6, v5
; GCN3-NEXT: v_add_u32_e32 v0, -1, v5
; GCN3-NEXT: s_or_b64 vcc, vcc, s[34:35]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v0, v3, vcc
; GCN3-NEXT: flat_atomic_cmpswap v0, v[1:2], v[4:5] offset:16 glc
Expand Down
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