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Fix legalizing FNEG and FABS with TypeSoftPromoteHalf #156343

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Fix legalizing FNEG and FABS with TypeSoftPromoteHalf #156343

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0403e98
Add more generic `half`/`bfloat` tests (NFC)
beetrees Sep 6, 2025
6cb6937
Fix legalizing `FNEG` and `FABS` with `TypeSoftPromoteHalf`
beetrees Sep 1, 2025
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26 changes: 24 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3313,7 +3313,6 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break;

// Unary FP Operations
case ISD::FABS:
case ISD::FACOS:
case ISD::FASIN:
case ISD::FATAN:
Expand All @@ -3329,7 +3328,6 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FNEARBYINT:
case ISD::FNEG:
case ISD::FREEZE:
case ISD::FRINT:
case ISD::FROUND:
Expand All @@ -3341,6 +3339,12 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FTAN:
case ISD::FTANH:
case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break;
case ISD::FABS:
R = SoftPromoteHalfRes_FABS(N);
break;
case ISD::FNEG:
R = SoftPromoteHalfRes_FNEG(N);
break;
case ISD::AssertNoFPClass:
R = SoftPromoteHalfRes_AssertNoFPClass(N);
break;
Expand Down Expand Up @@ -3670,6 +3674,24 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_UnaryOp(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FABS(SDNode *N) {
SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
SDLoc dl(N);

// Clear the sign bit.
return DAG.getNode(ISD::AND, dl, MVT::i16, Op,
DAG.getConstant(0x7fff, dl, MVT::i16));
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Could use APInt::getSignMask / getSignedMaxValue, but I suppose if this is really hardcoded to half it's easier to read this way. Not sure why so much code here hardcodes as half+i16

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TypeSoftPromoteHalf seems to be explicitly designed for only f16/bf16, so I think explicitly spelling out the constant makes it clearer.

}

SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FNEG(SDNode *N) {
SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
SDLoc dl(N);

// Invert the sign bit.
return DAG.getNode(ISD::XOR, dl, MVT::i16, Op,
DAG.getConstant(0x8000, dl, MVT::i16));
}

SDValue DAGTypeLegalizer::SoftPromoteHalfRes_AssertNoFPClass(SDNode *N) {
return GetSoftPromotedHalf(N->getOperand(0));
}
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -832,6 +832,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfRes_SELECT(SDNode *N);
SDValue SoftPromoteHalfRes_SELECT_CC(SDNode *N);
SDValue SoftPromoteHalfRes_UnaryOp(SDNode *N);
SDValue SoftPromoteHalfRes_FABS(SDNode *N);
SDValue SoftPromoteHalfRes_FNEG(SDNode *N);
SDValue SoftPromoteHalfRes_AssertNoFPClass(SDNode *N);
SDValue SoftPromoteHalfRes_XINT_TO_FP(SDNode *N);
SDValue SoftPromoteHalfRes_UNDEF(SDNode *N);
Expand Down
32 changes: 8 additions & 24 deletions llvm/test/CodeGen/AMDGPU/bf16.ll
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Expand Up @@ -19752,18 +19752,14 @@ define bfloat @v_fabs_bf16(bfloat %a) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fabs_bf16:
Expand Down Expand Up @@ -19946,21 +19942,15 @@ define bfloat @v_fneg_fabs_bf16(bfloat %a) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fneg_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fneg_fabs_bf16:
Expand Down Expand Up @@ -20002,23 +19992,17 @@ define amdgpu_ps i32 @s_fneg_fabs_bf16(bfloat inreg %a) {
; GCN-LABEL: s_fneg_fabs_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, s0
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_or_b32_e32 v0, 0x8000, v0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_bitset0_b32 s0, 31
; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_xor_b32 s0, s0, 0x80000000
; GCN-NEXT: s_lshr_b32 s0, s0, 16
; GCN-NEXT: ; return to shader part epilog
;
; GFX7-LABEL: s_fneg_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, s0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_or_b32_e32 v0, 0x8000, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
; GFX7-NEXT: s_bitset0_b32 s0, 31
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
; GFX7-NEXT: s_xor_b32 s0, s0, 0x80000000
; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fneg_fabs_bf16:
Expand Down
48 changes: 18 additions & 30 deletions llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
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Expand Up @@ -218,19 +218,11 @@ define amdgpu_kernel void @s_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s4, s3, 0xffff0000
; CI-NEXT: s_lshl_b32 s3, s3, 16
; CI-NEXT: s_and_b32 s5, s2, 0xffff0000
; CI-NEXT: v_mul_f32_e64 v0, 1.0, |s4|
; CI-NEXT: v_mul_f32_e64 v1, 1.0, |s3|
; CI-NEXT: v_mul_f32_e64 v2, 1.0, |s5|
; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; CI-NEXT: s_lshl_b32 s2, s2, 16
; CI-NEXT: v_alignbit_b32 v1, v0, v1, 16
; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; CI-NEXT: v_mul_f32_e64 v2, 1.0, |s2|
; CI-NEXT: v_alignbit_b32 v0, v0, v2, 16
; CI-NEXT: s_and_b32 s3, s3, 0x7fff7fff
; CI-NEXT: s_and_b32 s2, s2, 0x7fff7fff
; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
Expand Down Expand Up @@ -537,16 +529,15 @@ define amdgpu_kernel void @v_fabs_fold_self_v2bf16(ptr addrspace(1) %out, ptr ad
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: v_mul_f32_e64 v4, 1.0, |v3|
; CI-NEXT: v_mul_f32_e64 v5, 1.0, |v2|
; CI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; CI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; CI-NEXT: v_mul_f32_e32 v3, v4, v3
; CI-NEXT: v_mul_f32_e32 v2, v5, v2
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; CI-NEXT: v_alignbit_b32 v2, v3, v2, 16
; CI-NEXT: v_and_b32_e32 v3, 0x7fff, v2
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; CI-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; CI-NEXT: v_and_b32_e32 v2, 0x7fff0000, v2
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_mul_f32_e32 v2, v2, v5
; CI-NEXT: v_mul_f32_e32 v3, v3, v4
; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; CI-NEXT: v_alignbit_b32 v2, v2, v3, 16
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
;
Expand Down Expand Up @@ -898,16 +889,13 @@ define amdgpu_kernel void @v_extract_fabs_fold_v2bf16(ptr addrspace(1) %in) #0 {
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dword v0, v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; CI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; CI-NEXT: v_mul_f32_e64 v1, 1.0, |v1|
; CI-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; CI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; CI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; CI-NEXT: v_mul_f32_e32 v1, 4.0, v1
; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; CI-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; CI-NEXT: v_add_f32_e32 v0, 2.0, v0
; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; CI-NEXT: v_mul_f32_e32 v1, 4.0, v1
; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; CI-NEXT: flat_store_short v[0:1], v1
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: flat_store_short v[0:1], v0
Expand Down
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