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[AVR] Remove workarounds for instructions using Z register (NFCI) #156361

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Merged
merged 1 commit into from
Sep 4, 2025
Merged

[AVR] Remove workarounds for instructions using Z register (NFCI) #156361

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1 change: 1 addition & 0 deletions llvm/lib/Target/AVR/AVRInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,7 @@ class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<0> z;
bits<5> rd;

let Inst{15 - 12} = 0b1001;
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AVR/AVRInstrInfo.td
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Expand Up @@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {

let Defs = [R31R30] in
def SPMZPi : F16<0b1001010111111000, (outs), (ins ZREG:$z), "spm $z+", []>,
Requires<[HasSPMX]>;
Requires<[HasSPMX]> {
bits<0> z;
}
}

// Read data from IO location operations.
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AVR/CMakeLists.txt
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Expand Up @@ -6,8 +6,7 @@ tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
-ignore-non-decodable-operands)
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
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Expand Up @@ -91,6 +91,12 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}

static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(AVR::R31R30));
return MCDisassembler::Success;
}

static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
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17 changes: 0 additions & 17 deletions llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
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Expand Up @@ -101,23 +101,6 @@ const char *AVRInstPrinter::getPrettyRegisterName(MCRegister Reg,
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
if (MOI.RegClass == AVR::ZREGRegClassID) {
// Special case for the Z register, which sometimes doesn't have an operand
// in the MCInst.
O << "Z";
return;
}

if (OpNo >= MI->size()) {
// Not all operands are correctly disassembled at the moment. This means
// that some machine instructions won't have all the necessary operands
// set.
// To avoid asserting, print <unknown> instead until the necessary support
// has been implemented.
O << "<unknown>";
return;
}

const MCOperand &Op = MI->getOperand(OpNo);

if (Op.isReg()) {
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