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[RISCV][GISel] Add initial support for rvv intrinsics #156415

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[RISCV][GISel] Add initial support for rvv intrinsics #156415

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[RISCV][GISel] Add initial support for rvv intrinsics
jacquesguan Sep 2, 2025
623beec
Address comment
jacquesguan Sep 3, 2025
5851e4f
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jacquesguan Sep 3, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -707,6 +707,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();

if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
return true;
}
Comment on lines +711 to +713
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nit: llvm style prefers simple stmt bodies don't have {}s

Suggested change
if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
return true;
}
if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID))
return true;


switch (IntrinsicID) {
default:
return false;
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -38,6 +38,7 @@
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInstBuilder.h"
Expand Down Expand Up @@ -24700,6 +24701,12 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
Op == Instruction::Freeze || Op == Instruction::Store)
return false;

if (auto *II = dyn_cast<IntrinsicInst>(&Inst)) {
// Mark RVV intrinsic as supported.
if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(II->getIntrinsicID()))
return false;
}
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okay to keep them here though, because of the comment.


if (Inst.getType()->isScalableTy())
return true;

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33 changes: 0 additions & 33 deletions llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
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Expand Up @@ -2,39 +2,6 @@
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err


declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64)

; FALLBACK_WITH_REPORT_ERR: <unknown>:0:0: unable to translate instruction: call
; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg
define <vscale x 1 x i8> @scalable_arg(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 %2)

ret <vscale x 1 x i8> %a
}

; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call
; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_inst
define <vscale x 1 x i8> @scalable_inst(i64 %0) nounwind {
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
i64 %0)

ret <vscale x 1 x i8> %a
}

; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: alloca:
; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca
define void @scalable_alloca() #1 {
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