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[clang][RISCV] support BITINT with mixed-type #156592

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Merged
merged 8 commits into from
Oct 14, 2025
Merged

[clang][RISCV] support BITINT with mixed-type #156592

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0927005
[clang][RISCV] support BITINT with mixed-type
BeMg Jun 13, 2025
2629dac
Update format
BeMg Sep 3, 2025
db42cea
Refine the comment
BeMg Sep 8, 2025
a2c03fa
Drop the curly braces
BeMg Sep 8, 2025
ded0caf
Use Indirect when Size > 2 * XLEN
BeMg Sep 12, 2025
04d20af
Add test for RV32 and fforce-enable-int128
BeMg Sep 12, 2025
ca6cae9
Make RV64 _BitInt(32) always signext
BeMg Sep 22, 2025
5333575
!fixup update format
BeMg Sep 23, 2025
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16 changes: 9 additions & 7 deletions clang/lib/CodeGen/Targets/RISCV.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -680,14 +680,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
if (const auto *ED = Ty->getAsEnumDecl())
Ty = ED->getIntegerType();

// All integral types are promoted to XLen width
if (Size < XLen && Ty->isIntegralOrEnumerationType()) {
return extendType(Ty, CGT.ConvertType(Ty));
}

if (const auto *EIT = Ty->getAs<BitIntType>()) {
if (EIT->getNumBits() < XLen)
return extendType(Ty, CGT.ConvertType(Ty));
// FIXME: Maybe we should treat 32 as a special case and wait for
// the SPEC to decide.
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Copilot AI Sep 3, 2025

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The FIXME comment indicates uncertainty about handling 32-bit BitInt types and references waiting for a specification decision. This suggests the implementation may be incomplete or temporary for this specific case.

Suggested change
// FIXME: Maybe we should treat 32 as a special case and wait for
// the SPEC to decide.
// FIXME: The handling of 32-bit BitIntType is currently unspecified by the ABI.
// As a conservative approach, pass 32-bit BitIntType as direct without extension.
if (EIT->getNumBits() == 32)
return ABIArgInfo::getDirect();
if (EIT->getNumBits() < 32)
return extendType(Ty, CGT.ConvertType(Ty));

Copilot uses AI. Check for mistakes.
if (EIT->getNumBits() <= 2 * XLen)
return ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty));
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Can we call extendType here and remove the special case for 32 above? Looks like extendType will call ABIArgInfo::getExtend if its not the special case.

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There's something a bit strange happening here.

Ty: BitIntType 0xf7c7930 'unsigned _BitInt(17)

will be treated as 32 in

int TySize = getContext().getTypeSize(Ty);

If we use the extendType directly, unsigned _BitInt(17) will turn into a signed extension in this case.

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I'm guessing the call to getContext().getTypeSize(Ty) in that function returned the size rounded up to a byte.

I guess we can leave it how you have it then.

if (EIT->getNumBits() > 128 ||
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Is the existing code with hasInt128Type, correct for the new ABI?

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I think it's fine. And after this patch, I only assume updating the signed/unsigned extension between 0 and 2×XLEN.

The other part match the following rule.

0~XLEN      pass by value(reg)
XLEN~2xXLEN pass by value(reg pair)
> 2xXLEN    pass be reference(mem)

cc @kito-cheng

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Isn't the EIT->getNumBits() > 64 check always true after your change?

And it looks like for RV32, any size between 65 bits and 128 bits will pass directly when -fforce-enable-int128 is passed. Why is _BitInt behavior affected by -fforce-enable-int128?

(!getContext().getTargetInfo().hasInt128Type() &&
EIT->getNumBits() > 64))
Expand All @@ -696,6 +693,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
/*ByVal=*/false);
}

// All integral types are promoted to XLen width
if (Size < XLen && Ty->isIntegralOrEnumerationType()) {
return extendType(Ty, CGT.ConvertType(Ty));
}

return ABIArgInfo::getDirect();
}

Expand Down
233 changes: 233 additions & 0 deletions clang/test/CodeGen/RISCV/bitint.c
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@@ -0,0 +1,233 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV64
// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV32

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned
// RISCV64-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]
// RISCV64-NEXT: ret i17 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned
// RISCV32-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]
// RISCV32-NEXT: ret i17 [[ADD]]
//
unsigned _BitInt(17) test_bitint_17_add_unsigned(unsigned _BitInt(17) a, unsigned _BitInt(17) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_signed
// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
// RISCV64-NEXT: ret i17 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_signed
// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
// RISCV32-NEXT: ret i17 [[ADD]]
//
signed _BitInt(17) test_bitint_17_add_signed(signed _BitInt(17) a, signed _BitInt(17) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_default
// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
// RISCV64-NEXT: ret i17 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_default
// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
// RISCV32-NEXT: ret i17 [[ADD]]
//
_BitInt(17) test_bitint_17_add_default(_BitInt(17) a, _BitInt(17) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned
// RISCV64-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]
// RISCV64-NEXT: ret i32 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned
// RISCV32-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]
// RISCV32-NEXT: ret i32 [[ADD]]
//
unsigned _BitInt(32) test_bitint_32_add_unsigned(unsigned _BitInt(32) a, unsigned _BitInt(32) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_signed
// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
// RISCV64-NEXT: ret i32 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_signed
// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
// RISCV32-NEXT: ret i32 [[ADD]]
//
signed _BitInt(32) test_bitint_32_add_signed(signed _BitInt(32) a, signed _BitInt(32) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_default
// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
// RISCV64-NEXT: ret i32 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_default
// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
// RISCV32-NEXT: ret i32 [[ADD]]
//
_BitInt(32) test_bitint_32_add_default(_BitInt(32) a, _BitInt(32) b) {
return a + b;
}


// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned
// RISCV64-SAME: (i65 noundef zeroext [[A:%.*]], i65 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]
// RISCV64-NEXT: ret i65 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
// RISCV32-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: ret void
//
unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigned _BitInt(65) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_signed
// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
// RISCV64-NEXT: ret i65 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_signed
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: ret void
//
signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitInt(65) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_default
// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
// RISCV64-NEXT: ret i65 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_default
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
// RISCV32-NEXT: ret void
//
_BitInt(65) test_bitint_65_add_default(_BitInt(65) a, _BitInt(65) b) {
return a + b;
}


// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned
// RISCV64-SAME: (i77 noundef zeroext [[A:%.*]], i77 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]
// RISCV64-NEXT: ret i77 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
// RISCV32-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: ret void
//
unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigned _BitInt(77) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_signed
// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
// RISCV64-NEXT: ret i77 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_signed
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: ret void
//
signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitInt(77) b) {
return a + b;
}

// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_default
// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
// RISCV64-NEXT: entry:
// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
// RISCV64-NEXT: ret i77 [[ADD]]
//
// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_default
// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
// RISCV32-NEXT: entry:
// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128
// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
// RISCV32-NEXT: ret void
//
_BitInt(77) test_bitint_77_add_default(_BitInt(77) a, _BitInt(77) b) {
return a + b;
}
8 changes: 4 additions & 4 deletions clang/test/CodeGen/ext-int-cc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,8 @@ void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
// R600: define{{.*}} void @ParamPassing(ptr addrspace(5) byval(i128) align 8 %{{.+}}, i64 %{{.+}})
// ARC: define{{.*}} void @ParamPassing(ptr byval(i128) align 4 %{{.+}}, i64 inreg %{{.+}})
// XCORE: define{{.*}} void @ParamPassing(ptr byval(i128) align 4 %{{.+}}, i64 %{{.+}})
// RISCV64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
// RISCV32: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 %{{.+}})
// RISCV64: define{{.*}} void @ParamPassing(i128 signext %{{.+}}, i64 signext %{{.+}})
// RISCV32: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 signext %{{.+}})
// WASM: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
// SYSTEMZ: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 %{{.+}})
// PPC64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
Expand Down Expand Up @@ -79,8 +79,8 @@ void ParamPassing2(_BitInt(127) b, _BitInt(63) c) {}
// R600: define{{.*}} void @ParamPassing2(ptr addrspace(5) byval(i128) align 8 %{{.+}}, i63 %{{.+}})
// ARC: define{{.*}} void @ParamPassing2(ptr byval(i128) align 4 %{{.+}}, i63 inreg %{{.+}})
// XCORE: define{{.*}} void @ParamPassing2(ptr byval(i128) align 4 %{{.+}}, i63 %{{.+}})
// RISCV64: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 signext %{{.+}})
// RISCV32: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 %{{.+}})
// RISCV64: define{{.*}} void @ParamPassing2(i127 signext %{{.+}}, i63 signext %{{.+}})
// RISCV32: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 signext %{{.+}})
// WASM: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 %{{.+}})
// SYSTEMZ: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 signext %{{.+}})
// PPC64: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 signext %{{.+}})
Expand Down
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