Skip to content

[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer #156618

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Sep 4, 2025
Merged

[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer #156618

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
9bdf90a
Precommit tests
lukel97 Sep 3, 2025
4b860bb
[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOpt…
lukel97 Sep 3, 2025
712d2fc
Use correct VL operand with masked vleff
lukel97 Sep 3, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1464,6 +1464,15 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
assert((CommonVL->isImm() || CommonVL->getReg().isVirtual()) &&
"Expected VL to be an Imm or virtual Reg");

// If the VL is defined by a vleff that doesn't dominate MI, try using the
// vleff's AVL. It will be greater than or equal to the output VL.
if (CommonVL->isReg()) {
const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
if (RISCVInstrInfo::isFaultOnlyFirstLoad(*VLMI) &&
!MDT->dominates(VLMI, &MI))
CommonVL = VLMI->getOperand(4);
Copy link
Collaborator

@topperc topperc Sep 3, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this the correct operand number for a masked fault only first load?

Copy link
Contributor Author

@lukel97 lukel97 Sep 3, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

No, fixed in 712d2fc

Copy link
Collaborator

@preames preames Sep 3, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Good catch.

}

if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
return false;
Expand Down
46 changes: 46 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -603,4 +603,50 @@ body: |
$x10 = COPY %9
PseudoRET implicit $x10
...
---
name: vleff_imm
body: |
bb.0:
; CHECK-LABEL: name: vleff_imm
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...
---
name: vleff_reg_dominates
body: |
bb.0:
liveins: $x8
; CHECK-LABEL: name: vleff_reg_dominates
; CHECK: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %avl:gprnox0 = COPY $x8
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%avl:gprnox0 = COPY $x8
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...
---
name: vleff_reg_doesnt_dominate
body: |
bb.0:
liveins: $x8
; CHECK-LABEL: name: vleff_reg_doesnt_dominate
; CHECK: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %avl:gprnox0 = COPY $x8
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%avl:gprnox0 = COPY $x8
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...

Loading