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[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer #156618

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Merged
merged 3 commits into from
Sep 4, 2025
Merged

[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer #156618

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9bdf90a
Precommit tests
lukel97 Sep 3, 2025
4b860bb
[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOpt…
lukel97 Sep 3, 2025
712d2fc
Use correct VL operand with masked vleff
lukel97 Sep 3, 2025
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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1464,6 +1464,15 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
assert((CommonVL->isImm() || CommonVL->getReg().isVirtual()) &&
"Expected VL to be an Imm or virtual Reg");

// If the VL is defined by a vleff that doesn't dominate MI, try using the
// vleff's AVL. It will be greater than or equal to the output VL.
if (CommonVL->isReg()) {
const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
if (RISCVInstrInfo::isFaultOnlyFirstLoad(*VLMI) &&
!MDT->dominates(VLMI, &MI))
CommonVL = VLMI->getOperand(RISCVII::getVLOpNum(VLMI->getDesc()));
}

if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
return false;
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59 changes: 58 additions & 1 deletion llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -603,4 +603,61 @@ body: |
$x10 = COPY %9
PseudoRET implicit $x10
...

---
name: vleff_imm
body: |
bb.0:
; CHECK-LABEL: name: vleff_imm
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...
---
name: vleff_reg_dominates
body: |
bb.0:
liveins: $x8
; CHECK-LABEL: name: vleff_reg_dominates
; CHECK: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %avl:gprnox0 = COPY $x8
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%avl:gprnox0 = COPY $x8
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...
---
name: vleff_reg_doesnt_dominate
body: |
bb.0:
liveins: $x8
; CHECK-LABEL: name: vleff_reg_doesnt_dominate
; CHECK: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %avl:gprnox0 = COPY $x8
; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%avl:gprnox0 = COPY $x8
%y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...
---
name: vleff_mask_imm
body: |
bb.0:
; CHECK-LABEL: name: vleff_mask_imm
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */
%y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */
PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */
...