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[NFC][AMDGPU][SIMemoryLegalizer] remove effectively empty function #156806

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Merged
ssahasra merged 2 commits into from
Sep 12, 2025
Merged

[NFC][AMDGPU][SIMemoryLegalizer] remove effectively empty function #156806

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[NFC][AMDGPU][SIMemoryLegalizer] remove effectively empty function
ssahasra Sep 4, 2025
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Merge branch 'main' into users/ssahasra/cache-bypass
ssahasra Sep 12, 2025
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39 changes: 0 additions & 39 deletions llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -462,10 +462,6 @@ class SIGfx90ACacheControl : public SIGfx7CacheControl {
SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const override;

bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
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@Pierre-vh Pierre-vh Sep 4, 2025

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Can you add a comment to make it clear it's unimplemented by choice, not by mistake ?
Maybe comment out the declaration + add a small comment to say no additional bits are needed in this case

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@ssahasra ssahasra Sep 12, 2025

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I don't think that's necessary. There are other CacheControl classes in the same file that skip this function without a comment. And in general, that's the expected usage of a virtual function, right? If the derived class does not override the base class, then the base class applies by default.

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@jayfoad jayfoad Sep 12, 2025

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I agree.

SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const override;

bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const override;
Expand Down Expand Up @@ -1375,41 +1371,6 @@ bool SIGfx90ACacheControl::enableLoadCacheBypass(
return Changed;
}

bool SIGfx90ACacheControl::enableStoreCacheBypass(
const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const {
assert(!MI->mayLoad() && MI->mayStore());
bool Changed = false;

if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) {
switch (Scope) {
case SIAtomicScope::SYSTEM:
case SIAtomicScope::AGENT:
/// Do not set glc for store atomic operations as they implicitly write
/// through the L1 cache.
break;
case SIAtomicScope::WORKGROUP:
case SIAtomicScope::WAVEFRONT:
case SIAtomicScope::SINGLETHREAD:
// No cache to bypass. Store atomics implicitly write through the L1
// cache.
break;
default:
llvm_unreachable("Unsupported synchronization scope");
}
}

/// The scratch address space does not need the global memory caches
/// to be bypassed as all memory operations by the same thread are
/// sequentially consistent, and no other thread can access scratch
/// memory.

/// Other address spaces do not have a cache.

return Changed;
}

bool SIGfx90ACacheControl::enableRMWCacheBypass(
const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope,
Expand Down