Skip to content

X86: Use LiveRegUnits in findDeadCallerSavedReg #156817

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Sep 9, 2025
Merged

X86: Use LiveRegUnits in findDeadCallerSavedReg #156817

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c831a2a
X86: Use LiveRegUnits in findDeadCallerSavedReg
arsenm Sep 4, 2025
8b22709
Update llvm/lib/Target/X86/X86RegisterInfo.cpp
arsenm Sep 9, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 13 additions & 15 deletions llvm/lib/Target/X86/X86RegisterInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1002,8 +1002,6 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
if (MF->callsEHReturn())
return 0;

const TargetRegisterClass &AvailableRegs = *getGPRsForTailCall(*MF);

if (MBBI == MBB.end())
return 0;

Expand All @@ -1025,20 +1023,20 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
case X86::TCRETURNmi64:
case X86::EH_RETURN:
case X86::EH_RETURN64: {
SmallSet<uint16_t, 8> Uses;
for (MachineOperand &MO : MBBI->operands()) {
if (!MO.isReg() || MO.isDef())
continue;
Register Reg = MO.getReg();
if (!Reg)
continue;
for (MCRegAliasIterator AI(Reg, this, true); AI.isValid(); ++AI)
Uses.insert(*AI);
LiveRegUnits LRU(*this);
LRU.addLiveOuts(MBB);
LRU.stepBackward(*MBBI);

// FIXME: Why do we need to special case this register? Is it missing from
// return implicit uses?
LRU.removeReg(X86::RIP);
Copy link
Contributor

@phoebewang phoebewang Sep 9, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Isn't X86::GR64_NOSPRegClass excluding RIP?

Copy link
Contributor Author

@arsenm arsenm Sep 9, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Not sure if that's the class constraint an all of these instructions. This is attempting to reproduce the existing logic

Copy link
Contributor

@phoebewang phoebewang Sep 9, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/X86/X86RegisterInfo.td#L685


const TargetRegisterClass &RC =
Is64Bit ? X86::GR64_NOSPRegClass : X86::GR32_NOSPRegClass;
for (MCRegister Reg : RC) {
if (LRU.available(Reg))
return Reg;
}

for (auto CS : AvailableRegs)
if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
return CS;
}
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ define i32 @csr6_alloc16(ptr %argv) {
; LIN-NEXT: .cfi_def_cfa_offset 32
; LIN-NEXT: pop2 %rbp, %r15
; LIN-NEXT: .cfi_def_cfa_offset 16
; LIN-NEXT: popq %rcx
; LIN-NEXT: popq %rax
; LIN-NEXT: .cfi_def_cfa_offset 8
; LIN-NEXT: retq
;
Expand Down Expand Up @@ -116,7 +116,7 @@ define i32 @csr6_alloc16(ptr %argv) {
; LIN-PPX-NEXT: .cfi_def_cfa_offset 32
; LIN-PPX-NEXT: pop2p %rbp, %r15
; LIN-PPX-NEXT: .cfi_def_cfa_offset 16
; LIN-PPX-NEXT: popq %rcx
; LIN-PPX-NEXT: popq %rax
; LIN-PPX-NEXT: .cfi_def_cfa_offset 8
; LIN-PPX-NEXT: retq
;
Expand Down Expand Up @@ -180,7 +180,7 @@ define i32 @csr6_alloc16(ptr %argv) {
; WIN-NEXT: pop2 %rbp, %rbx
; WIN-NEXT: pop2 %r13, %r12
; WIN-NEXT: pop2 %r15, %r14
; WIN-NEXT: popq %rcx
; WIN-NEXT: popq %rax
; WIN-NEXT: .seh_endepilogue
; WIN-NEXT: retq
; WIN-NEXT: .seh_endproc
Expand Down Expand Up @@ -211,7 +211,7 @@ define i32 @csr6_alloc16(ptr %argv) {
; WIN-PPX-NEXT: pop2p %rbp, %rbx
; WIN-PPX-NEXT: pop2p %r13, %r12
; WIN-PPX-NEXT: pop2p %r15, %r14
; WIN-PPX-NEXT: popq %rcx
; WIN-PPX-NEXT: popq %rax
; WIN-PPX-NEXT: .seh_endepilogue
; WIN-PPX-NEXT: retq
; WIN-PPX-NEXT: .seh_endproc
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/lvi-hardening-ret.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,9 +41,9 @@ entry:
%add = add nsw i32 %0, %1
ret i32 %add
; CHECK-NOT: retq
; CHECK: popq %rcx
; CHECK: popq %rsi
; CHECK-NEXT: lfence
; CHECK-NEXT: jmpq *%rcx
; CHECK-NEXT: jmpq *%rsi
}

; Function Attrs: noinline nounwind optnone uwtable
Expand All @@ -52,9 +52,9 @@ define dso_local preserve_mostcc void @preserve_most() #0 {
entry:
ret void
; CHECK-NOT: retq
; CHECK: popq %rax
; CHECK: popq %r11
; CHECK-NEXT: lfence
; CHECK-NEXT: jmpq *%rax
; CHECK-NEXT: jmpq *%r11
}

; Function Attrs: noinline nounwind optnone uwtable
Expand All @@ -63,9 +63,9 @@ define dso_local preserve_allcc void @preserve_all() #0 {
entry:
ret void
; CHECK-NOT: retq
; CHECK: popq %rax
; CHECK: popq %r11
; CHECK-NEXT: lfence
; CHECK-NEXT: jmpq *%rax
; CHECK-NEXT: jmpq *%r11
}

define { i64, i128 } @ret_i64_i128() #0 {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/pr40289-64bit.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,5 +6,5 @@ define cc 92 < 9 x i64 > @clobber() {
ret < 9 x i64 > undef
; CHECK-LABEL: clobber:
; CHECK-NOT: popq %rsp
; CHECK: addq $8, %rsp
; CHECK: popq %rax
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/pr40289.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,5 +6,5 @@ define < 3 x i32 > @clobber() {
ret < 3 x i32 > undef
; CHECK-LABEL: clobber:
; CHECK-NOT: popl %esp
; CHECK: addl $4, %esp
; CHECK: popl %eax
}