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merged 4 commits into from
Sep 4, 2025
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[NFC][TableGen] Adopt CodeGenInstruction::getName() #156968

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452d06e
[NFC][TableGen] Adopt `CodeGenInstruction::getName()`
jurahul Sep 4, 2025
927fac1
Update llvm/utils/TableGen/AsmWriterEmitter.cpp
jurahul Sep 4, 2025
5c367b7
Update llvm/utils/TableGen/CompressInstEmitter.cpp
jurahul Sep 4, 2025
8bfb688
Merge branch 'main' into nfc_cgi_getName
jurahul Sep 4, 2025
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7 changes: 3 additions & 4 deletions llvm/utils/TableGen/AsmMatcherEmitter.cpp
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Expand Up @@ -1545,7 +1545,7 @@ void AsmMatcherInfo::buildInfo() {

// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instructions we consider.
if (!StringRef(CGI->TheDef->getName()).starts_with(MatchPrefix))
if (!StringRef(CGI->getName()).starts_with(MatchPrefix))
continue;

// Ignore "codegen only" instructions.
Expand Down Expand Up @@ -1578,8 +1578,7 @@ void AsmMatcherInfo::buildInfo() {
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instruction aliases we consider, based on the target
// instruction.
if (!StringRef(Alias->ResultInst->TheDef->getName())
.starts_with(MatchPrefix))
if (!StringRef(Alias->ResultInst->getName()).starts_with(MatchPrefix))
continue;

StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");
Expand Down Expand Up @@ -3562,7 +3561,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
OS << " { " << *StringTable.GetStringOffset(LenMnemonic) << " /* "
<< MI->Mnemonic << " */, " << Target.getInstNamespace()
<< "::" << MI->getResultInst()->TheDef->getName() << ", "
<< "::" << MI->getResultInst()->getName() << ", "
<< MI->ConversionFnKind << ", ";

// Write the required features mask.
Expand Down
19 changes: 9 additions & 10 deletions llvm/utils/TableGen/AsmWriterEmitter.cpp
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Expand Up @@ -129,11 +129,10 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
}
}

O << " case " << FirstInst.CGI->Namespace
<< "::" << FirstInst.CGI->TheDef->getName() << ":\n";
O << " case " << FirstInst.CGI->Namespace << "::" << FirstInst.CGI->getName()
<< ":\n";
for (const AsmWriterInst &AWI : SimilarInsts)
O << " case " << AWI.CGI->Namespace << "::" << AWI.CGI->TheDef->getName()
<< ":\n";
O << " case " << AWI.CGI->Namespace << "::" << AWI.CGI->getName() << ":\n";
for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
if (i != DifferingOperand) {
// If the operand is the same for all instructions, just print it.
Expand All @@ -145,12 +144,12 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
OpsToPrint.emplace_back(FirstInst.CGI->Namespace.str() +
"::" + FirstInst.CGI->TheDef->getName().str(),
"::" + FirstInst.CGI->getName().str(),
FirstInst.Operands[i]);

for (const AsmWriterInst &AWI : SimilarInsts) {
OpsToPrint.emplace_back(AWI.CGI->Namespace.str() +
"::" + AWI.CGI->TheDef->getName().str(),
"::" + AWI.CGI->getName().str(),
AWI.Operands[i]);
}
std::reverse(OpsToPrint.begin(), OpsToPrint.end());
Expand Down Expand Up @@ -188,11 +187,11 @@ void AsmWriterEmitter::FindUniqueOperandCommands(
if (I != UniqueOperandCommands.end()) {
size_t idx = I - UniqueOperandCommands.begin();
InstrsForCase[idx] += ", ";
InstrsForCase[idx] += Inst.CGI->TheDef->getName();
InstrsForCase[idx] += Inst.CGI->getName();
InstIdxs[idx].push_back(i);
} else {
UniqueOperandCommands.push_back(std::move(Command));
InstrsForCase.push_back(Inst.CGI->TheDef->getName().str());
InstrsForCase.push_back(Inst.CGI->getName().str());
InstIdxs.emplace_back();
InstIdxs.back().push_back(i);

Expand Down Expand Up @@ -451,7 +450,7 @@ void AsmWriterEmitter::EmitGetMnemonic(
<< "[] = {\n";
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
<< NumberedInstructions[i]->TheDef->getName() << "\n";
<< NumberedInstructions[i]->getName() << "\n";
}
O << " };\n\n";
// Emit string to combine the individual table lookups.
Expand Down Expand Up @@ -1317,7 +1316,7 @@ AsmWriterEmitter::AsmWriterEmitter(const RecordKeeper &R)
NumberedInstructions = Target.getInstructions();

for (const auto &[Idx, I] : enumerate(NumberedInstructions)) {
if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
if (!I->AsmString.empty() && I->getName() != "PHI")
Instructions.emplace_back(*I, Idx, Variant);
}
}
Expand Down
14 changes: 7 additions & 7 deletions llvm/utils/TableGen/Common/AsmWriterInst.cpp
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Expand Up @@ -94,7 +94,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Non-supported escaped character found in instruction '" +
CGI.TheDef->getName() + "'!");
CGI.getName() + "'!");
}
LastEmitted = DollarPos + 2;
continue;
Expand Down Expand Up @@ -135,7 +135,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Reached end of string before terminating curly brace in '" +
CGI.TheDef->getName() + "'");
CGI.getName() + "'");

// Look for a modifier string.
if (AsmString[VarEnd] == ':') {
Expand All @@ -144,28 +144,28 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Reached end of string before terminating curly brace in '" +
CGI.TheDef->getName() + "'");
CGI.getName() + "'");

std::string::size_type ModifierStart = VarEnd;
while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
++VarEnd;
Modifier = AsmString.substr(ModifierStart, VarEnd - ModifierStart);
if (Modifier.empty())
PrintFatalError(CGI.TheDef->getLoc(),
"Bad operand modifier name in '" +
CGI.TheDef->getName() + "'");
"Bad operand modifier name in '" + CGI.getName() +
"'");
}

if (AsmString[VarEnd] != '}')
PrintFatalError(
CGI.TheDef->getLoc(),
"Variable name beginning with '{' did not end with '}' in '" +
CGI.TheDef->getName() + "'");
CGI.getName() + "'");
++VarEnd;
}
if (VarName.empty() && Modifier.empty())
PrintFatalError(CGI.TheDef->getLoc(),
"Stray '$' in '" + CGI.TheDef->getName() +
"Stray '$' in '" + CGI.getName() +
"' asm string, maybe you want $$?");

if (VarName.empty()) {
Expand Down
19 changes: 9 additions & 10 deletions llvm/utils/TableGen/Common/CodeGenSchedule.cpp
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Expand Up @@ -134,7 +134,7 @@ struct InstRegexOp : public SetTheory::Operator {

// The generic opcodes are unsorted, handle them manually.
for (auto *Inst : Generics) {
StringRef InstName = Inst->TheDef->getName();
StringRef InstName = Inst->getName();
if (InstName.starts_with(Prefix) &&
(!Regexpr || Regexpr->match(InstName.substr(Prefix.size())))) {
Elts.insert(Inst->TheDef);
Expand All @@ -147,11 +147,10 @@ struct InstRegexOp : public SetTheory::Operator {
// sorted by name. Find the sub-ranges that start with our prefix.
struct Comp {
bool operator()(const CodeGenInstruction *LHS, StringRef RHS) {
return LHS->TheDef->getName() < RHS;
return LHS->getName() < RHS;
}
bool operator()(StringRef LHS, const CodeGenInstruction *RHS) {
return LHS < RHS->TheDef->getName() &&
!RHS->TheDef->getName().starts_with(LHS);
return LHS < RHS->getName() && !RHS->getName().starts_with(LHS);
}
};
auto Range1 =
Expand All @@ -162,7 +161,7 @@ struct InstRegexOp : public SetTheory::Operator {
// For these ranges we know that instruction names start with the prefix.
// Check if there's a regex that needs to be checked.
const auto HandleNonGeneric = [&](const CodeGenInstruction *Inst) {
StringRef InstName = Inst->TheDef->getName();
StringRef InstName = Inst->getName();
if (!Regexpr || Regexpr->match(InstName.substr(Prefix.size()))) {
Elts.insert(Inst->TheDef);
NumMatches++;
Expand Down Expand Up @@ -862,12 +861,12 @@ void CodeGenSchedModels::collectSchedClasses() {
dbgs()
<< "\n+++ ITINERARIES and/or MACHINE MODELS (collectSchedClasses) +++\n");
for (const CodeGenInstruction *Inst : Target.getInstructions()) {
StringRef InstName = Inst->TheDef->getName();
StringRef InstName = Inst->getName();
unsigned SCIdx = getSchedClassIdx(*Inst);
if (!SCIdx) {
LLVM_DEBUG({
if (!Inst->hasNoSchedulingInfo)
dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
dbgs() << "No machine model for " << Inst->getName() << '\n';
});
continue;
}
Expand Down Expand Up @@ -916,7 +915,7 @@ void CodeGenSchedModels::collectSchedClasses() {
if (!llvm::is_contained(ProcIndices, 0)) {
for (const CodeGenProcModel &PM : ProcModels) {
if (!llvm::is_contained(ProcIndices, PM.Index))
dbgs() << "No machine model for " << Inst->TheDef->getName()
dbgs() << "No machine model for " << Inst->getName()
<< " on processor " << PM.ModelName << '\n';
}
}
Expand Down Expand Up @@ -1932,7 +1931,7 @@ void CodeGenSchedModels::checkCompleteness() {
if (Inst->TheDef->isValueUnset("SchedRW")) {
PrintError(Inst->TheDef->getLoc(),
"No schedule information for instruction '" +
Inst->TheDef->getName() + "' in SchedMachineModel '" +
Inst->getName() + "' in SchedMachineModel '" +
ProcModel.ModelDef->getName() + "'");
Complete = false;
}
Expand All @@ -1953,7 +1952,7 @@ void CodeGenSchedModels::checkCompleteness() {
if (I == InstRWs.end()) {
PrintError(Inst->TheDef->getLoc(), "'" + ProcModel.ModelName +
"' lacks information for '" +
Inst->TheDef->getName() + "'");
Inst->getName() + "'");
Complete = false;
}
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Common/DAGISelMatcher.cpp
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Expand Up @@ -284,7 +284,7 @@ void EmitNodeXFormMatcher::printImpl(raw_ostream &OS, indent Indent) const {
void EmitNodeMatcherCommon::printImpl(raw_ostream &OS, indent Indent) const {
OS << Indent;
OS << (isa<MorphNodeToMatcher>(this) ? "MorphNodeTo: " : "EmitNode: ")
<< CGI.Namespace << "::" << CGI.TheDef->getName() << ": <todo flags> ";
<< CGI.Namespace << "::" << CGI.getName() << ": <todo flags> ";

for (MVT::SimpleValueType VT : VTs)
OS << ' ' << getEnumName(VT);
Expand Down
20 changes: 9 additions & 11 deletions llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
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Expand Up @@ -1455,9 +1455,8 @@ RecordAndValue
InstructionOpcodeMatcher::getInstValue(const CodeGenInstruction *I) const {
const auto VI = OpcodeValues.find(I);
if (VI != OpcodeValues.end())
return {MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()),
VI->second};
return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName());
return {MatchTable::NamedValue(2, I->Namespace, I->getName()), VI->second};
return MatchTable::NamedValue(2, I->Namespace, I->getName());
}

void InstructionOpcodeMatcher::initOpcodeValuesMap(
Expand All @@ -1474,9 +1473,8 @@ RecordAndValue InstructionOpcodeMatcher::getValue() const {
const CodeGenInstruction *I = Insts[0];
const auto VI = OpcodeValues.find(I);
if (VI != OpcodeValues.end())
return {MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()),
VI->second};
return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName());
return {MatchTable::NamedValue(2, I->Namespace, I->getName()), VI->second};
return MatchTable::NamedValue(2, I->Namespace, I->getName());
}

void InstructionOpcodeMatcher::emitPredicateOpcodes(MatchTable &Table,
Expand All @@ -1503,17 +1501,17 @@ bool InstructionOpcodeMatcher::isHigherPriorityThan(
// using instruction frequency information to improve compile time.
if (const InstructionOpcodeMatcher *BO =
dyn_cast<InstructionOpcodeMatcher>(&B))
return Insts[0]->TheDef->getName() < BO->Insts[0]->TheDef->getName();
return Insts[0]->getName() < BO->Insts[0]->getName();

return false;
}

bool InstructionOpcodeMatcher::isConstantInstruction() const {
return Insts.size() == 1 && Insts[0]->TheDef->getName() == "G_CONSTANT";
return Insts.size() == 1 && Insts[0]->getName() == "G_CONSTANT";
}

StringRef InstructionOpcodeMatcher::getOpcode() const {
return Insts[0]->TheDef->getName();
return Insts[0]->getName();
}

bool InstructionOpcodeMatcher::isVariadicNumOperands() const {
Expand Down Expand Up @@ -2245,7 +2243,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
<< MatchTable::Comment("RecycleInsnID")
<< MatchTable::ULEB128Value(RecycleInsnID)
<< MatchTable::Comment("Opcode")
<< MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName())
<< MatchTable::NamedValue(2, I->Namespace, I->getName())
<< MatchTable::LineBreak;

if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) {
Expand Down Expand Up @@ -2292,7 +2290,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
}

Table << MatchTable::Comment("Opcode")
<< MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName())
<< MatchTable::NamedValue(2, I->Namespace, I->getName())
<< MatchTable::LineBreak;

for (const auto &Renderer : OperandRenderers)
Expand Down
9 changes: 3 additions & 6 deletions llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
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Expand Up @@ -168,8 +168,7 @@ void Pattern::printImpl(raw_ostream &OS, bool PrintName,
void AnyOpcodePattern::print(raw_ostream &OS, bool PrintName) const {
printImpl(OS, PrintName, [&OS, this]() {
OS << "["
<< join(map_range(Insts,
[](const auto *I) { return I->TheDef->getName(); }),
<< join(map_range(Insts, [](const auto *I) { return I->getName(); }),
", ")
<< "]";
});
Expand Down Expand Up @@ -366,7 +365,7 @@ void MIFlagsInfo::addCopyFlag(StringRef InstName) { CopyF.insert(InstName); }
//===- CodeGenInstructionPattern ------------------------------------------===//

bool CodeGenInstructionPattern::is(StringRef OpcodeName) const {
return I.TheDef->getName() == OpcodeName;
return I.getName() == OpcodeName;
}

bool CodeGenInstructionPattern::isVariadic() const {
Expand Down Expand Up @@ -416,9 +415,7 @@ MIFlagsInfo &CodeGenInstructionPattern::getOrCreateMIFlagsInfo() {
return *FI;
}

StringRef CodeGenInstructionPattern::getInstName() const {
return I.TheDef->getName();
}
StringRef CodeGenInstructionPattern::getInstName() const { return I.getName(); }

void CodeGenInstructionPattern::printExtras(raw_ostream &OS) const {
if (isIntrinsic())
Expand Down
14 changes: 7 additions & 7 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
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Expand Up @@ -237,7 +237,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
// Source instructions can have at most 1 tied operand.
if (IsSourceInst && (OpNo - DAGOpNo > 1))
PrintFatalError(Rec->getLoc(),
"Input operands for Inst '" + Inst.TheDef->getName() +
"Input operands for Inst '" + Inst.getName() +
"' and input Dag operand count mismatch");

continue;
Expand All @@ -249,7 +249,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
OpndRec = cast<DefInit>(Opnd.MIOperandInfo->getArg(SubOp))->getDef();

if (DAGOpNo >= Dag->getNumArgs())
PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
PrintFatalError(Rec->getLoc(), "Inst '" + Inst.getName() +
"' and Dag operand count mismatch");

if (const auto *DI = dyn_cast<DefInit>(Dag->getArg(DAGOpNo))) {
Expand Down Expand Up @@ -328,7 +328,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,

// We shouldn't have extra Dag operands.
if (DAGOpNo != Dag->getNumArgs())
PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
PrintFatalError(Rec->getLoc(), "Inst '" + Inst.getName() +
"' and Dag operand count mismatch");
}

Expand Down Expand Up @@ -590,8 +590,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
const CompressPat &RHS) {
if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
return (LHS.Source.getName() < RHS.Source.getName());
return (LHS.Dest.getName() < RHS.Dest.getName());
});

// A list of MCOperandPredicates for all operands in use, and the reverse map.
Expand Down Expand Up @@ -678,7 +678,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
CompressOrCheck ? CompressPat.DestOperandMap
: CompressPat.SourceOperandMap;

CurOp = Source.TheDef->getName();
CurOp = Source.getName();
// Check current and previous opcode to decide to continue or end a case.
if (CurOp != PrevOp) {
if (!PrevOp.empty()) {
Expand Down Expand Up @@ -768,7 +768,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setOpcode(" << TargetName
<< "::" << Dest.TheDef->getName() << ");\n";
<< "::" << Dest.getName() << ");\n";
OpNo = 0;
for (const auto &DestOperand : Dest.Operands) {
CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
Expand Down
5 changes: 2 additions & 3 deletions llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
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Expand Up @@ -1662,8 +1662,7 @@ bool CombineRuleBuilder::emitMatchPattern(CodeExpansions &CE,

const bool IsUsingCustomCXXAction = hasOnlyCXXApplyPatterns();
for (const CodeGenInstruction *CGI : AOP.insts()) {
auto &M = addRuleMatcher(Alts, "wip_match_opcode '" +
CGI->TheDef->getName() + "'");
auto &M = addRuleMatcher(Alts, "wip_match_opcode '" + CGI->getName() + "'");

InstructionMatcher &IM = M.addInstructionMatcher(AOP.getName());
declareInstExpansion(CE, IM, AOP.getName());
Expand Down Expand Up @@ -2201,7 +2200,7 @@ bool CombineRuleBuilder::emitBuiltinApplyPattern(

bool isLiteralImm(const InstructionPattern &P, unsigned OpIdx) {
if (const auto *CGP = dyn_cast<CodeGenInstructionPattern>(&P)) {
StringRef InstName = CGP->getInst().TheDef->getName();
StringRef InstName = CGP->getInst().getName();
return (InstName == "G_CONSTANT" || InstName == "G_FCONSTANT") &&
OpIdx == 1;
}
Expand Down
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