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arsenm merged 2 commits into from
Sep 16, 2025
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PPC: Split 64bit target feature into 64bit and 64bit-support #157206

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b5ab7a9
PPC: Move definitions of predicates with features
arsenm Sep 5, 2025
0d4d26a
PPC: Split 64bit target feature into 64bit and 64bit-support
arsenm Sep 5, 2025
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70 changes: 56 additions & 14 deletions llvm/lib/Target/PowerPC/PPC.td
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Original file line number Diff line number Diff line change
Expand Up @@ -58,8 +58,13 @@ def DirectivePwrFuture

// Specifies that the selected CPU supports 64-bit instructions, regardless of
// whether we are in 32-bit or 64-bit mode.
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
def Feature64BitSupport : SubtargetFeature<"64bit-support", "Has64BitSupport", "true",
"Supports 64-bit instructions">;
// 64-bit is enabled.
def Feature64Bit : SubtargetFeature<"64bit", "IsPPC64", "true",
"Enable 64-bit mode",
[Feature64BitSupport]>;

def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
def FeatureModernAIXAs
: SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
Expand All @@ -85,7 +90,7 @@ def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
"Enable SPE instructions",
[FeatureHardFloat]>;
def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
"Enable Embedded Floating-Point APU 2 instructions",
[FeatureSPE]>;
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
Expand Down Expand Up @@ -353,6 +358,43 @@ def FeaturePredictableSelectIsExpensive :
def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
"MFLR is a fast instruction">;

//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
def IsBookE : Predicate<"Subtarget->isBookE()">;
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">;
def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">;
def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">;
def IsE500 : Predicate<"Subtarget->isE500()">;
def HasSPE : Predicate<"Subtarget->hasSPE()">;
def HasICBT : Predicate<"Subtarget->hasICBT()">;
def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;
def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">;
def NoNaNsFPMath
: Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;

// AIX assembler may not be modern enough to support some extended mne.
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;


// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
// less error prone and easier to read.
Expand Down Expand Up @@ -392,7 +434,7 @@ def ProcessorFeatures {
FeaturePOPCNTD,
FeatureCMPB,
FeatureLDBRX,
Feature64Bit,
Feature64BitSupport,
/* Feature64BitRegs, */
FeatureBPERMD,
FeatureExtDiv,
Expand Down Expand Up @@ -630,13 +672,13 @@ def : ProcessorModel<"970", G5Model,
[Directive970, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt,
FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */,
Feature64BitSupport /*, Feature64BitRegs */,
FeatureMFTB]>;
def : ProcessorModel<"g5", G5Model,
[Directive970, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
FeatureFRES, FeatureFRSQRTE,
Feature64Bit /*, Feature64BitRegs */,
Feature64BitSupport /*, Feature64BitRegs */,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"e500", PPCE500Model,
[DirectiveE500,
Expand All @@ -657,41 +699,41 @@ def : ProcessorModel<"a2", PPCA2Model,
FeatureSTFIWX, FeatureLFIWAX,
FeatureFPRND, FeatureFPCVT, FeatureISEL,
FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
Feature64BitSupport /*, Feature64BitRegs */, FeatureMFTB,
FeatureISA2_06]>;
def : ProcessorModel<"pwr3", G5Model,
[DirectivePwr3, FeatureAltivec,
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
FeatureSTFIWX, Feature64Bit]>;
FeatureSTFIWX, Feature64BitSupport]>;
def : ProcessorModel<"pwr4", G5Model,
[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
FeatureSTFIWX, Feature64BitSupport, FeatureMFTB]>;
def : ProcessorModel<"pwr5", G5Model,
[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
FeatureFSqrt, FeatureFRE, FeatureFRES,
FeatureFRSQRTE, FeatureFRSQRTES,
FeatureSTFIWX, Feature64Bit,
FeatureSTFIWX, Feature64BitSupport,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"pwr5x", G5Model,
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
FeatureFSqrt, FeatureFRE, FeatureFRES,
FeatureFRSQRTE, FeatureFRSQRTES,
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
FeatureSTFIWX, FeatureFPRND, Feature64BitSupport,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"pwr6", G5Model,
[DirectivePwr6, FeatureAltivec,
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
FeatureFPRND, Feature64BitSupport /*, Feature64BitRegs */,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"pwr6x", G5Model,
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
FeatureFPRND, Feature64Bit,
FeatureFPRND, Feature64BitSupport,
FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
Expand All @@ -709,7 +751,7 @@ def : ProcessorModel<"ppc64", G5Model,
[Directive64, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
FeatureFRSQRTE, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */,
Feature64BitSupport /*, Feature64BitRegs */,
FeatureMFTB]>;
def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;

Expand Down
36 changes: 0 additions & 36 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -713,42 +713,6 @@ let WantsParent = true in {
def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">;
}

//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
def IsBookE : Predicate<"Subtarget->isBookE()">;
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">;
def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">;
def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">;
def IsE500 : Predicate<"Subtarget->isE500()">;
def HasSPE : Predicate<"Subtarget->hasSPE()">;
def HasICBT : Predicate<"Subtarget->hasICBT()">;
def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;
def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">;
def NoNaNsFPMath
: Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;

// AIX assembler may not be modern enough to support some extended mne.
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;

//===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions.
multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
Expand Down
7 changes: 2 additions & 5 deletions llvm/lib/Target/PowerPC/PPCSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -54,10 +54,8 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,

PPCSubtarget::PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, const PPCTargetMachine &TM)
: PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS),
IsPPC64(getTargetTriple().getArch() == Triple::ppc64 ||
getTargetTriple().getArch() == Triple::ppc64le),
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
: PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TM(TM),
FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
InstrInfo(*this), TLInfo(TM, *this) {
TSInfo = std::make_unique<PPCSelectionDAGInfo>();

Expand Down Expand Up @@ -247,7 +245,6 @@ CodeModel::Model PPCSubtarget::getCodeModel(const TargetMachine &TM,
}

bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }

bool PPCSubtarget::isUsingPCRelativeCalls() const {
return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
Expand Down
5 changes: 0 additions & 5 deletions llvm/lib/Target/PowerPC/PPCSubtarget.h
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Expand Up @@ -93,7 +93,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
/// Which cpu directive was used.
unsigned CPUDirective;

bool IsPPC64;
bool IsLittleEndian;

POPCNTDKind HasPOPCNTD;
Expand Down Expand Up @@ -167,10 +166,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);

public:
/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
///
bool isPPC64() const;

// useSoftFloat - Return true if soft-float option is turned on.
bool useSoftFloat() const {
if (isAIXABI() && !HasHardFloat)
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/PowerPC/i64_fp.ll
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@@ -1,17 +1,17 @@
; fcfid and fctid should be generated when the 64bit feature is enabled, but not
; otherwise.

; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit-support | \
; RUN: grep fcfid
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit-support | \
; RUN: grep fctidz
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
; RUN: grep fcfid
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \
; RUN: grep fctidz
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit-support | \
; RUN: not grep fcfid
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit-support | \
; RUN: not grep fctidz
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \
; RUN: not grep fcfid
Expand Down
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