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[Headers][X86] Add constexpr support for some AVX[512] intrinsics. #157260

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Merged
RKSimon merged 31 commits into from
Sep 7, 2025
Merged

[Headers][X86] Add constexpr support for some AVX[512] intrinsics. #157260

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6a3ea16
_mm_cvtepi64_pd
moorabbit Sep 4, 2025
c62d862
_mm_mask_cvtepi64_pd
moorabbit Sep 4, 2025
a6a93ba
_mm_maskz_cvtepi64_pd
moorabbit Sep 4, 2025
7dfa2c5
_mm_cvtepu64_pd
moorabbit Sep 4, 2025
b6c59f0
_mm_mask_cvtepu64_pd
moorabbit Sep 4, 2025
da06e42
_mm_maskz_cvtepu64_pd
moorabbit Sep 4, 2025
54ce1e6
_mm256_cvtepi64_pd
moorabbit Sep 4, 2025
aa736dd
_mm256_mask_cvtepi64_pd
moorabbit Sep 4, 2025
ee4b2e4
_mm256_maskz_cvtepi64_pd
moorabbit Sep 4, 2025
9413ce2
_mm256_cvtepu64_pd
moorabbit Sep 4, 2025
5cb9160
_mm256_mask_cvtepu64_pd
moorabbit Sep 4, 2025
92743c9
_mm256_maskz_cvtepu64_pd
moorabbit Sep 4, 2025
2e1a427
_mm256_cvtepi64_ps
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4a5bdcc
_mm256_mask_cvtepi64_ps
moorabbit Sep 5, 2025
f203d64
_mm256_maskz_cvtepi64_ps
moorabbit Sep 5, 2025
d06bb90
_mm256_cvtepu64_ps
moorabbit Sep 5, 2025
5cc0637
_mm256_mask_cvtepu64_ps
moorabbit Sep 5, 2025
357b4ab
_mm256_maskz_cvtepu64_ps
moorabbit Sep 5, 2025
8bbacba
_mm_cvtepi16_ph
moorabbit Sep 5, 2025
7886cd1
_mm_mask_cvtepi16_ph
moorabbit Sep 5, 2025
b9021da
_mm_maskz_cvtepi16_ph
moorabbit Sep 5, 2025
2e912c9
_mm_set1_ph
moorabbit Sep 5, 2025
24b8898
_mm_cvtepu16_ph
moorabbit Sep 5, 2025
626ef1b
_mm_mask_cvtepu16_ph
moorabbit Sep 5, 2025
30c5f9c
_mm_maskz_cvtepu16_ph
moorabbit Sep 5, 2025
294330c
_mm256_cvtepi16_ph
moorabbit Sep 5, 2025
373bced
_mm256_mask_cvtepi16_ph
moorabbit Sep 5, 2025
8310f59
_mm256_set1_ph
moorabbit Sep 5, 2025
4bf0e6c
minor
moorabbit Sep 6, 2025
6c5dc4e
_mm256_maskz_cvtepi16_ph
moorabbit Sep 6, 2025
f8db4f0
Merge branch 'main' into constexpr-avx512-intrinsics-part-3
RKSimon Sep 7, 2025
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72 changes: 36 additions & 36 deletions clang/lib/Headers/avx512vldqintrin.h
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Original file line number Diff line number Diff line change
Expand Up @@ -460,39 +460,39 @@ _mm256_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
(__mmask8) __U);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_cvtepi64_pd (__m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_cvtepi64_pd(__m128i __A) {
return (__m128d)__builtin_convertvector((__v2di)__A, __v2df);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_cvtepi64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_mask_cvtepi64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepi64_pd(__A),
(__v2df)__W);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_cvtepi64_pd (__mmask8 __U, __m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_maskz_cvtepi64_pd(__mmask8 __U, __m128i __A) {
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepi64_pd(__A),
(__v2df)_mm_setzero_pd());
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_cvtepi64_pd (__m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtepi64_pd(__m256i __A) {
return (__m256d)__builtin_convertvector((__v4di)__A, __v4df);
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_mask_cvtepi64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_mask_cvtepi64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepi64_pd(__A),
(__v4df)__W);
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtepi64_pd (__mmask8 __U, __m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_maskz_cvtepi64_pd(__mmask8 __U, __m256i __A) {
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepi64_pd(__A),
(__v4df)_mm256_setzero_pd());
Expand All @@ -519,20 +519,20 @@ _mm_maskz_cvtepi64_ps (__mmask8 __U, __m128i __A) {
(__mmask8) __U);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_cvtepi64_ps (__m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtepi64_ps(__m256i __A) {
return (__m128)__builtin_convertvector((__v4di)__A, __v4sf);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_mask_cvtepi64_ps (__m128 __W, __mmask8 __U, __m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_mask_cvtepi64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm256_cvtepi64_ps(__A),
(__v4sf)__W);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtepi64_ps (__mmask8 __U, __m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_maskz_cvtepi64_ps(__mmask8 __U, __m256i __A) {
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm256_cvtepi64_ps(__A),
(__v4sf)_mm_setzero_ps());
Expand Down Expand Up @@ -706,39 +706,39 @@ _mm256_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
(__mmask8) __U);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_cvtepu64_pd (__m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_cvtepu64_pd(__m128i __A) {
return (__m128d)__builtin_convertvector((__v2du)__A, __v2df);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_cvtepu64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_mask_cvtepu64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepu64_pd(__A),
(__v2df)__W);
}

static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_cvtepu64_pd (__mmask8 __U, __m128i __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_maskz_cvtepu64_pd(__mmask8 __U, __m128i __A) {
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepu64_pd(__A),
(__v2df)_mm_setzero_pd());
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_cvtepu64_pd (__m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtepu64_pd(__m256i __A) {
return (__m256d)__builtin_convertvector((__v4du)__A, __v4df);
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_mask_cvtepu64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_mask_cvtepu64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepu64_pd(__A),
(__v4df)__W);
}

static __inline__ __m256d __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtepu64_pd (__mmask8 __U, __m256i __A) {
static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_maskz_cvtepu64_pd(__mmask8 __U, __m256i __A) {
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepu64_pd(__A),
(__v4df)_mm256_setzero_pd());
Expand All @@ -765,20 +765,20 @@ _mm_maskz_cvtepu64_ps (__mmask8 __U, __m128i __A) {
(__mmask8) __U);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_cvtepu64_ps (__m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtepu64_ps(__m256i __A) {
return (__m128)__builtin_convertvector((__v4du)__A, __v4sf);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_mask_cvtepu64_ps (__m128 __W, __mmask8 __U, __m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_mask_cvtepu64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm256_cvtepu64_ps(__A),
(__v4sf)__W);
}

static __inline__ __m128 __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtepu64_ps (__mmask8 __U, __m256i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_maskz_cvtepu64_ps(__mmask8 __U, __m256i __A) {
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm256_cvtepu64_ps(__A),
(__v4sf)_mm_setzero_ps());
Expand Down
26 changes: 15 additions & 11 deletions clang/lib/Headers/avx512vlfp16intrin.h
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -46,11 +46,13 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_set_sh(_Float16 __h) {
return __extension__(__m128h){__h, 0, 0, 0, 0, 0, 0, 0};
}

static __inline __m128h __DEFAULT_FN_ATTRS128 _mm_set1_ph(_Float16 __h) {
static __inline __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_set1_ph(_Float16 __h) {
return (__m128h)(__v8hf){__h, __h, __h, __h, __h, __h, __h, __h};
}

static __inline __m256h __DEFAULT_FN_ATTRS256 _mm256_set1_ph(_Float16 __h) {
static __inline __m256h __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_set1_ph(_Float16 __h) {
return (__m256h)(__v16hf){__h, __h, __h, __h, __h, __h, __h, __h,
__h, __h, __h, __h, __h, __h, __h, __h};
}
Expand Down Expand Up @@ -807,34 +809,35 @@ _mm256_maskz_cvttph_epi16(__mmask16 __U, __m256h __A) {
(__v16hf)__A, (__v16hi)_mm256_setzero_si256(), (__mmask16)__U);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtepi16_ph(__m128i __A) {
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_cvtepi16_ph(__m128i __A) {
return (__m128h) __builtin_convertvector((__v8hi)__A, __v8hf);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_mask_cvtepi16_ph(__m128h __W, __mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_selectph_128(
(__mmask8)__U, (__v8hf)_mm_cvtepi16_ph(__A), (__v8hf)__W);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_maskz_cvtepi16_ph(__mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_selectph_128(
(__mmask8)__U, (__v8hf)_mm_cvtepi16_ph(__A), (__v8hf)_mm_setzero_ph());
}

static __inline__ __m256h __DEFAULT_FN_ATTRS256
static __inline__ __m256h __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtepi16_ph(__m256i __A) {
return (__m256h) __builtin_convertvector((__v16hi)__A, __v16hf);
}

static __inline__ __m256h __DEFAULT_FN_ATTRS256
static __inline__ __m256h __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_mask_cvtepi16_ph(__m256h __W, __mmask16 __U, __m256i __A) {
return (__m256h)__builtin_ia32_selectph_256(
(__mmask16)__U, (__v16hf)_mm256_cvtepi16_ph(__A), (__v16hf)__W);
}

static __inline__ __m256h __DEFAULT_FN_ATTRS256
static __inline__ __m256h __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_maskz_cvtepi16_ph(__mmask16 __U, __m256i __A) {
return (__m256h)__builtin_ia32_selectph_256((__mmask16)__U,
(__v16hf)_mm256_cvtepi16_ph(__A),
Expand Down Expand Up @@ -911,17 +914,18 @@ _mm256_maskz_cvttph_epu16(__mmask16 __U, __m256h __A) {
(__v16hf)__A, (__v16hu)_mm256_setzero_si256(), (__mmask16)__U);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtepu16_ph(__m128i __A) {
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_cvtepu16_ph(__m128i __A) {
return (__m128h) __builtin_convertvector((__v8hu)__A, __v8hf);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_mask_cvtepu16_ph(__m128h __W, __mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_selectph_128(
(__mmask8)__U, (__v8hf)_mm_cvtepu16_ph(__A), (__v8hf)__W);
}

static __inline__ __m128h __DEFAULT_FN_ATTRS128
static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_maskz_cvtepu16_ph(__mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_selectph_128(
(__mmask8)__U, (__v8hf)_mm_cvtepu16_ph(__A), (__v8hf)_mm_setzero_ph());
Expand Down
36 changes: 36 additions & 0 deletions clang/test/CodeGen/X86/avx512vldq-builtins.c
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Original file line number Diff line number Diff line change
Expand Up @@ -440,40 +440,52 @@ __m128d test_mm_cvtepi64_pd(__m128i __A) {
return _mm_cvtepi64_pd(__A);
}

TEST_CONSTEXPR(match_m128d(_mm_cvtepi64_pd((__m128i)(__v2di){-1, -1}), -1.0, -1.0));

__m128d test_mm_mask_cvtepi64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: test_mm_mask_cvtepi64_pd
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_mask_cvtepi64_pd(__W, __U, __A);
}

TEST_CONSTEXPR(match_m128d(_mm_mask_cvtepi64_pd((__m128d){-777.0, -777.0}, /*01=*/0x1, (__m128i)(__v2di){-1, -1}), -1.0, -777.0));

__m128d test_mm_maskz_cvtepi64_pd(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: test_mm_maskz_cvtepi64_pd
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_maskz_cvtepi64_pd(__U, __A);
}

TEST_CONSTEXPR(match_m128d(_mm_maskz_cvtepi64_pd(/*01=*/0x1, (__m128i)(__v2di){-1, -1}), -1.0, 0.0));

__m256d test_mm256_cvtepi64_pd(__m256i __A) {
// CHECK-LABEL: test_mm256_cvtepi64_pd
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
return _mm256_cvtepi64_pd(__A);
}

TEST_CONSTEXPR(match_m256d(_mm256_cvtepi64_pd((__m256i)(__v4di){-1, -1, 2, 2}), -1.0, -1.0, 2.0, 2.0));

__m256d test_mm256_mask_cvtepi64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_mask_cvtepi64_pd
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_mask_cvtepi64_pd(__W, __U, __A);
}

TEST_CONSTEXPR(match_m256d(_mm256_mask_cvtepi64_pd((__m256d){-777.0, -777.0, -777.0, -777.0}, /*1100*/0xc, (__m256i)(__v4di){-1, -1, 2, 2}), -777.0, -777.0, 2.0, 2.0));

__m256d test_mm256_maskz_cvtepi64_pd(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_maskz_cvtepi64_pd
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_maskz_cvtepi64_pd(__U, __A);
}

TEST_CONSTEXPR(match_m256d(_mm256_maskz_cvtepi64_pd(/*1100*/0xc, (__m256i)(__v4di){-1, -1, 2, 2}), 0.0, 0.0, 2.0, 2.0));

__m128 test_mm_cvtepi64_ps(__m128i __A) {
// CHECK-LABEL: test_mm_cvtepi64_ps
// CHECK: @llvm.x86.avx512.mask.cvtqq2ps.128
Expand All @@ -498,20 +510,26 @@ __m128 test_mm256_cvtepi64_ps(__m256i __A) {
return _mm256_cvtepi64_ps(__A);
}

TEST_CONSTEXPR(match_m128(_mm256_cvtepi64_ps((__m256i)(__v4di){-1, -1, 2, 2}), -1.0f, -1.0f, 2.0f, 2.0f));

__m128 test_mm256_mask_cvtepi64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_mask_cvtepi64_ps
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x float>
// select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm256_mask_cvtepi64_ps(__W, __U, __A);
}

TEST_CONSTEXPR(match_m128(_mm256_mask_cvtepi64_ps((__m128){-777.0f, -777.0f, -777.0f, -777.0f}, /*1010=*/0xa, (__m256i)(__v4di){-1, -1, 2, 2}), -777.0f, -1.0f, -777.0f, 2.0f));

__m128 test_mm256_maskz_cvtepi64_ps(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_maskz_cvtepi64_ps
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x float>
// select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm256_maskz_cvtepi64_ps(__U, __A);
}

TEST_CONSTEXPR(match_m128(_mm256_maskz_cvtepi64_ps(/*1010=*/0xa, (__m256i)(__v4di){-1, -1, 2, 2}), 0.0f, -1.0f, 0.0f, 2.0f));

__m128i test_mm_cvttpd_epi64(__m128d __A) {
// CHECK-LABEL: test_mm_cvttpd_epi64
// CHECK: @llvm.x86.avx512.mask.cvttpd2qq.128
Expand Down Expand Up @@ -662,40 +680,52 @@ __m128d test_mm_cvtepu64_pd(__m128i __A) {
return _mm_cvtepu64_pd(__A);
}

TEST_CONSTEXPR(match_m128d(_mm_cvtepu64_pd((__m128i)(__v2du){1, 1}), 1.0, 1.0));

__m128d test_mm_mask_cvtepu64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: test_mm_mask_cvtepu64_pd
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_mask_cvtepu64_pd(__W, __U, __A);
}

TEST_CONSTEXPR(match_m128d(_mm_mask_cvtepu64_pd((__m128d){-777.0, -777.0}, /*01=*/0x1, (__m128i)(__v2du){1, 1}), 1.0, -777.0));

__m128d test_mm_maskz_cvtepu64_pd(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: test_mm_maskz_cvtepu64_pd
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_maskz_cvtepu64_pd(__U, __A);
}

TEST_CONSTEXPR(match_m128d(_mm_maskz_cvtepu64_pd(/*01=*/0x1, (__m128i)(__v2du){1, 1}), 1.0, 0.0));

__m256d test_mm256_cvtepu64_pd(__m256i __A) {
// CHECK-LABEL: test_mm256_cvtepu64_pd
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
return _mm256_cvtepu64_pd(__A);
}

TEST_CONSTEXPR(match_m256d(_mm256_cvtepu64_pd((__m256i)(__v4du){1, 1, 2, 2}), 1.0, 1.0, 2.0, 2.0));

__m256d test_mm256_mask_cvtepu64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_mask_cvtepu64_pd
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_mask_cvtepu64_pd(__W, __U, __A);
}

TEST_CONSTEXPR(match_m256d(_mm256_mask_cvtepu64_pd((__m256d){-777.0, -777.0, -777.0, -777.0}, /*1100*/0xc, (__m256i)(__v4du){1, 1, 2, 2}), -777.0, -777.0, 2.0, 2.0));

__m256d test_mm256_maskz_cvtepu64_pd(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_maskz_cvtepu64_pd
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_maskz_cvtepu64_pd(__U, __A);
}

TEST_CONSTEXPR(match_m256d(_mm256_maskz_cvtepu64_pd(/*1100*/0xc, (__m256i)(__v4du){1, 1, 2, 2}), 0.0, 0.0, 2.0, 2.0));

__m128 test_mm_cvtepu64_ps(__m128i __A) {
// CHECK-LABEL: test_mm_cvtepu64_ps
// CHECK: @llvm.x86.avx512.mask.cvtuqq2ps.128
Expand All @@ -720,20 +750,26 @@ __m128 test_mm256_cvtepu64_ps(__m256i __A) {
return _mm256_cvtepu64_ps(__A);
}

TEST_CONSTEXPR(match_m128(_mm256_cvtepu64_ps((__m256i)(__v4du){1, 1, 2, 2}), 1.0f, 1.0f, 2.0f, 2.0f));

__m128 test_mm256_mask_cvtepu64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_mask_cvtepu64_ps
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm256_mask_cvtepu64_ps(__W, __U, __A);
}

TEST_CONSTEXPR(match_m128(_mm256_mask_cvtepu64_ps((__m128){-777.0f, -777.0f, -777.0f, -777.0f}, /*1010=*/0xa, (__m256i)(__v4du){1, 1, 2, 2}), -777.0f, 1.0f, -777.0f, 2.0f));

__m128 test_mm256_maskz_cvtepu64_ps(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: test_mm256_maskz_cvtepu64_ps
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm256_maskz_cvtepu64_ps(__U, __A);
}

TEST_CONSTEXPR(match_m128(_mm256_maskz_cvtepu64_ps(/*1010=*/0xa, (__m256i)(__v4du){1, 1, 2, 2}), 0.0f, 1.0f, 0.0f, 2.0f));

__m128d test_mm_range_pd(__m128d __A, __m128d __B) {
// CHECK-LABEL: test_mm_range_pd
// CHECK: @llvm.x86.avx512.mask.range.pd.128
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