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[RISCV][GlobalIsel] Lower G_FMINIMUMNUM, G_FMAXIMUMNUM #157295

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Merged
merged 2 commits into from
Sep 11, 2025
Merged

[RISCV][GlobalIsel] Lower G_FMINIMUMNUM, G_FMAXIMUMNUM #157295

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3f9a5f6
[RISCV][GlobalIsel] Lower G_FMINIMUMNUM, G_FMAXIMUMNUM
sunshaoce Sep 6, 2025
b9b8a37
Remove unused code
sunshaoce Sep 10, 2025
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6 changes: 6 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -487,6 +487,10 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
RTLIBCASE(FMIN_F);
case TargetOpcode::G_FMAXNUM:
RTLIBCASE(FMAX_F);
case TargetOpcode::G_FMINIMUMNUM:
RTLIBCASE(FMINIMUM_NUM_F);
case TargetOpcode::G_FMAXIMUMNUM:
RTLIBCASE(FMAXIMUM_NUM_F);
case TargetOpcode::G_FSQRT:
RTLIBCASE(SQRT_F);
case TargetOpcode::G_FRINT:
Expand Down Expand Up @@ -1307,6 +1311,8 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
case TargetOpcode::G_FFLOOR:
case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FRINT:
case TargetOpcode::G_FNEARBYINT:
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/Utils.cpp
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Expand Up @@ -775,6 +775,10 @@ llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
return minimum(C1, C2);
case TargetOpcode::G_FMAXIMUM:
return maximum(C1, C2);
case TargetOpcode::G_FMINIMUMNUM:
return minimumnum(C1, C2);
case TargetOpcode::G_FMAXIMUMNUM:
return maximumnum(C1, C2);
case TargetOpcode::G_FMINNUM_IEEE:
case TargetOpcode::G_FMAXNUM_IEEE:
// FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
Expand Down Expand Up @@ -1758,9 +1762,11 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FMA:
case TargetOpcode::G_FMAD:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FMAXIMUMNUM:
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMAXNUM_IEEE:
case TargetOpcode::G_FMINIMUM:
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMINNUM_IEEE:
case TargetOpcode::G_FMUL:
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -507,8 +507,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
// FP Operations

// FIXME: Support s128 for rv32 when libcall handling is able to use sret.
getActionDefinitionsBuilder(
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM})
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT,
G_FMAXNUM, G_FMINNUM, G_FMAXIMUMNUM,
G_FMINIMUMNUM})
.legalFor(ST.hasStdExtF(), {s32})
.legalFor(ST.hasStdExtD(), {s64})
.legalFor(ST.hasStdExtZfh(), {s16})
Expand Down
122 changes: 90 additions & 32 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
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Expand Up @@ -363,6 +363,64 @@ define double @fmax_d(double %a, double %b) nounwind {
ret double %1
}

declare double @llvm.minimumnum.f64(double, double)

define double @fminimumnum_d(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fminimumnum_d:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fminimumnum_d:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fminimum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fminimumnum_d:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fminimum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.minimumnum.f64(double %a, double %b)
ret double %1
}

declare double @llvm.maximumnum.f64(double, double)

define double @fmaximumnum_d(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fmaximumnum_d:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmaximumnum_d:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fmaximum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fmaximumnum_d:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmaximum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.maximumnum.f64(double %a, double %b)
ret double %1
}

declare double @llvm.fma.f64(double, double, double)

define double @fmadd_d(double %a, double %b, double %c) nounwind {
Expand Down Expand Up @@ -420,8 +478,8 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s3, a3
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: lui a1, %hi(.LCPI12_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI12_0)
; RV32I-NEXT: lui a1, %hi(.LCPI14_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI14_0)
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: mv a1, a5
Expand Down Expand Up @@ -450,8 +508,8 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a0, %hi(.LCPI12_0)
; RV64I-NEXT: ld a1, %lo(.LCPI12_0)(a0)
; RV64I-NEXT: lui a0, %hi(.LCPI14_0)
; RV64I-NEXT: ld a1, %lo(.LCPI14_0)(a0)
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: li a1, -1
Expand Down Expand Up @@ -503,8 +561,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI13_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI13_0)
; RV32I-NEXT: lui a2, %hi(.LCPI15_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI15_0)
; RV32I-NEXT: lw s3, 0(a2)
; RV32I-NEXT: lw s4, 4(a2)
; RV32I-NEXT: mv s5, a5
Expand Down Expand Up @@ -548,8 +606,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI13_0)
; RV64I-NEXT: ld s1, %lo(.LCPI13_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI15_0)
; RV64I-NEXT: ld s1, %lo(.LCPI15_0)(a1)
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __adddf3
Expand Down Expand Up @@ -613,8 +671,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI14_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI14_0)
; RV32I-NEXT: lui a2, %hi(.LCPI16_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI16_0)
; RV32I-NEXT: lw s3, 0(a2)
; RV32I-NEXT: lw s4, 4(a2)
; RV32I-NEXT: mv s5, a5
Expand Down Expand Up @@ -658,8 +716,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI14_0)
; RV64I-NEXT: ld s1, %lo(.LCPI14_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI16_0)
; RV64I-NEXT: ld s1, %lo(.LCPI16_0)(a1)
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __adddf3
Expand Down Expand Up @@ -783,8 +841,8 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI17_0)
; RV32I-NEXT: addi a3, a2, %lo(.LCPI17_0)
; RV32I-NEXT: lui a2, %hi(.LCPI19_0)
; RV32I-NEXT: addi a3, a2, %lo(.LCPI19_0)
; RV32I-NEXT: lw a2, 0(a3)
; RV32I-NEXT: lw a3, 4(a3)
; RV32I-NEXT: mv s3, a5
Expand All @@ -811,8 +869,8 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI19_0)
; RV64I-NEXT: ld a1, %lo(.LCPI19_0)(a1)
; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: li a1, -1
Expand Down Expand Up @@ -860,8 +918,8 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI18_0)
; RV32I-NEXT: addi a3, a2, %lo(.LCPI18_0)
; RV32I-NEXT: lui a2, %hi(.LCPI20_0)
; RV32I-NEXT: addi a3, a2, %lo(.LCPI20_0)
; RV32I-NEXT: lw a2, 0(a3)
; RV32I-NEXT: lw a3, 4(a3)
; RV32I-NEXT: mv s3, a5
Expand Down Expand Up @@ -890,8 +948,8 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI18_0)
; RV64I-NEXT: ld a1, %lo(.LCPI18_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI20_0)
; RV64I-NEXT: ld a1, %lo(.LCPI20_0)(a1)
; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: li a1, -1
Expand Down Expand Up @@ -985,8 +1043,8 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s3, a3
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: lui a1, %hi(.LCPI20_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI20_0)
; RV32I-NEXT: lui a1, %hi(.LCPI22_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI22_0)
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: mv a1, a5
Expand Down Expand Up @@ -1020,8 +1078,8 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a0, %hi(.LCPI20_0)
; RV64I-NEXT: ld a1, %lo(.LCPI20_0)(a0)
; RV64I-NEXT: lui a0, %hi(.LCPI22_0)
; RV64I-NEXT: ld a1, %lo(.LCPI22_0)(a0)
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: mv s2, a0
Expand Down Expand Up @@ -1080,8 +1138,8 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI21_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI21_0)
; RV32I-NEXT: lui a2, %hi(.LCPI23_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI23_0)
; RV32I-NEXT: lw s3, 0(a2)
; RV32I-NEXT: lw s4, 4(a2)
; RV32I-NEXT: mv s5, a5
Expand Down Expand Up @@ -1135,8 +1193,8 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI21_0)
; RV64I-NEXT: ld s1, %lo(.LCPI21_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI23_0)
; RV64I-NEXT: ld s1, %lo(.LCPI23_0)(a1)
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __adddf3
Expand Down Expand Up @@ -1205,8 +1263,8 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a3
; RV32I-NEXT: mv s2, a4
; RV32I-NEXT: lui a2, %hi(.LCPI22_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI22_0)
; RV32I-NEXT: lui a2, %hi(.LCPI24_0)
; RV32I-NEXT: addi a2, a2, %lo(.LCPI24_0)
; RV32I-NEXT: lw s3, 0(a2)
; RV32I-NEXT: lw s4, 4(a2)
; RV32I-NEXT: mv s5, a5
Expand Down Expand Up @@ -1251,8 +1309,8 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI22_0)
; RV64I-NEXT: ld s1, %lo(.LCPI22_0)(a1)
; RV64I-NEXT: lui a1, %hi(.LCPI24_0)
; RV64I-NEXT: ld s1, %lo(.LCPI24_0)(a1)
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __adddf3
Expand Down
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