Skip to content

[BPF] Remove skb operand of LD_ABS/LD_IND instructions #157344

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 8, 2025
+6 −45
Merged

[BPF] Remove skb operand of LD_ABS/LD_IND instructions #157344

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
21 changes: 0 additions & 21 deletions llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -193,27 +193,6 @@ void BPFDAGToDAGISel::Select(SDNode *Node) {
switch (Opcode) {
default:
break;
case ISD::INTRINSIC_W_CHAIN: {
unsigned IntNo = Node->getConstantOperandVal(1);
switch (IntNo) {
case Intrinsic::bpf_load_byte:
case Intrinsic::bpf_load_half:
case Intrinsic::bpf_load_word: {
SDLoc DL(Node);
SDValue Chain = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
SDValue Skb = Node->getOperand(2);
SDValue N3 = Node->getOperand(3);

SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());
Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);
break;
}
}
break;
}

case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
EVT VT = Node->getValueType(0);
Expand Down
10 changes: 4 additions & 6 deletions llvm/lib/Target/BPF/BPFInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1189,10 +1189,9 @@ let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
: TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value,
(outs),
(ins GPR:$skb, i64imm:$imm),
(outs), (ins i64imm:$imm),
"r0 = *("#OpcodeStr#" *)skb[$imm]",
[(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
[(set R0, (OpNode R6, i64immSExt32:$imm))]> {
bits<32> imm;

let Inst{31-0} = imm;
Expand All @@ -1201,10 +1200,9 @@ class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>

class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
: TYPE_LD_ST<BPF_IND.Value, SizeOp.Value,
(outs),
(ins GPR:$skb, GPR:$val),
(outs), (ins GPR:$val),
"r0 = *("#OpcodeStr#" *)skb[$val]",
[(set R0, (OpNode GPR:$skb, GPR:$val))]> {
[(set R0, (OpNode R6, GPR:$val))]> {
bits<4> val;

let Inst{55-52} = val;
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/BPF/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,7 @@ tablegen(LLVM BPFGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler
-ignore-non-decodable-operands)
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
Expand Down
12 changes: 0 additions & 12 deletions llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -205,18 +205,6 @@ DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
Op.setImm(Make_64(Hi, Op.getImm()));
break;
}
case BPF::LD_ABS_B:
case BPF::LD_ABS_H:
case BPF::LD_ABS_W:
case BPF::LD_IND_B:
case BPF::LD_IND_H:
case BPF::LD_IND_W: {
auto Op = Instr.getOperand(0);
Instr.clear();
Instr.addOperand(MCOperand::createReg(BPF::R6));
Instr.addOperand(Op);
break;
}
}

return Result;
Expand Down
5 changes: 1 addition & 4 deletions utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2307,10 +2307,7 @@ llvm_target_lib_list = [lib for lib in [
"lib/Target/BPF/BPFGenCallingConv.inc": ["-gen-callingconv"],
"lib/Target/BPF/BPFGenDAGISel.inc": ["-gen-dag-isel"],
"lib/Target/BPF/BPFGenGlobalISel.inc": ["-gen-global-isel"],
"lib/Target/BPF/BPFGenDisassemblerTables.inc": [
"-gen-disassembler",
"-ignore-non-decodable-operands",
],
"lib/Target/BPF/BPFGenDisassemblerTables.inc": ["-gen-disassembler"],
"lib/Target/BPF/BPFGenMCCodeEmitter.inc": ["-gen-emitter"],
"lib/Target/BPF/BPFGenInstrInfo.inc": ["-gen-instr-info"],
"lib/Target/BPF/BPFGenRegisterInfo.inc": ["-gen-register-info"],
Expand Down