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[RISCV][GISel] Support select vx, vf form rvv intrinsics #157398

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Sep 19, 2025
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[RISCV][GISel] Support select vx, vf form rvv intrinsics #157398

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[RISCV][GISel] Support select vx, vf form rvv intrinsics
jacquesguan Sep 8, 2025
3845e02
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jacquesguan Sep 17, 2025
808109a
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jacquesguan Sep 18, 2025
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163 changes: 89 additions & 74 deletions llvm/include/llvm/IR/IntrinsicsRISCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,7 @@ class RISCVVIntrinsic {
Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
bits<4> ScalarOperand = NoScalarOperand;
bits<5> VLOperand = NoVLOperand;
bit IsFPIntrinsic = 0;
}

let TargetPrefix = "riscv" in {
Expand Down Expand Up @@ -1442,14 +1443,15 @@ let TargetPrefix = "riscv" in {
defm vwmaccus : RISCVTernaryWide;
defm vwmaccsu : RISCVTernaryWide;

defm vfadd : RISCVBinaryAAXRoundingMode;
defm vfsub : RISCVBinaryAAXRoundingMode;
defm vfrsub : RISCVBinaryAAXRoundingMode;

defm vfwadd : RISCVBinaryABXRoundingMode;
defm vfwsub : RISCVBinaryABXRoundingMode;
defm vfwadd_w : RISCVBinaryAAXRoundingMode;
defm vfwsub_w : RISCVBinaryAAXRoundingMode;
let IsFPIntrinsic = 1 in {
defm vfadd : RISCVBinaryAAXRoundingMode;
defm vfsub : RISCVBinaryAAXRoundingMode;
defm vfrsub : RISCVBinaryAAXRoundingMode;
defm vfwadd : RISCVBinaryABXRoundingMode;
defm vfwsub : RISCVBinaryABXRoundingMode;
defm vfwadd_w : RISCVBinaryAAXRoundingMode;
defm vfwsub_w : RISCVBinaryAAXRoundingMode;
}

defm vsaddu : RISCVSaturatingBinaryAAX;
defm vsadd : RISCVSaturatingBinaryAAX;
Expand Down Expand Up @@ -1484,6 +1486,7 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
let IsFPIntrinsic = 1;
}

def int_riscv_vmv_x_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
Expand All @@ -1506,51 +1509,57 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
let IsFPIntrinsic = 1;
}

defm vfmul : RISCVBinaryAAXRoundingMode;
defm vfdiv : RISCVBinaryAAXRoundingMode;
defm vfrdiv : RISCVBinaryAAXRoundingMode;
let IsFPIntrinsic = 1 in {
defm vfmul : RISCVBinaryAAXRoundingMode;
defm vfdiv : RISCVBinaryAAXRoundingMode;
defm vfrdiv : RISCVBinaryAAXRoundingMode;

defm vfwmul : RISCVBinaryABXRoundingMode;
defm vfwmul : RISCVBinaryABXRoundingMode;

defm vfmacc : RISCVTernaryAAXARoundingMode;
defm vfnmacc : RISCVTernaryAAXARoundingMode;
defm vfmsac : RISCVTernaryAAXARoundingMode;
defm vfnmsac : RISCVTernaryAAXARoundingMode;
defm vfmadd : RISCVTernaryAAXARoundingMode;
defm vfnmadd : RISCVTernaryAAXARoundingMode;
defm vfmsub : RISCVTernaryAAXARoundingMode;
defm vfnmsub : RISCVTernaryAAXARoundingMode;
defm vfmacc : RISCVTernaryAAXARoundingMode;
defm vfnmacc : RISCVTernaryAAXARoundingMode;
defm vfmsac : RISCVTernaryAAXARoundingMode;
defm vfnmsac : RISCVTernaryAAXARoundingMode;
defm vfmadd : RISCVTernaryAAXARoundingMode;
defm vfnmadd : RISCVTernaryAAXARoundingMode;
defm vfmsub : RISCVTernaryAAXARoundingMode;
defm vfnmsub : RISCVTernaryAAXARoundingMode;

defm vfwmacc : RISCVTernaryWideRoundingMode;
defm vfwmaccbf16 : RISCVTernaryWideRoundingMode;
defm vfwnmacc : RISCVTernaryWideRoundingMode;
defm vfwmsac : RISCVTernaryWideRoundingMode;
defm vfwnmsac : RISCVTernaryWideRoundingMode;
defm vfwmacc : RISCVTernaryWideRoundingMode;
defm vfwmaccbf16 : RISCVTernaryWideRoundingMode;
defm vfwnmacc : RISCVTernaryWideRoundingMode;
defm vfwmsac : RISCVTernaryWideRoundingMode;
defm vfwnmsac : RISCVTernaryWideRoundingMode;

defm vfsqrt : RISCVUnaryAARoundingMode;
defm vfrsqrt7 : RISCVUnaryAA;
defm vfrec7 : RISCVUnaryAARoundingMode;
defm vfsqrt : RISCVUnaryAARoundingMode;
defm vfrsqrt7 : RISCVUnaryAA;
defm vfrec7 : RISCVUnaryAARoundingMode;

defm vfmin : RISCVBinaryAAX;
defm vfmax : RISCVBinaryAAX;
defm vfmin : RISCVBinaryAAX;
defm vfmax : RISCVBinaryAAX;

defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX;
defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX;

defm vfclass : RISCVClassify;
defm vfclass : RISCVClassify;

defm vfmerge : RISCVBinaryWithV0;
defm vfmerge : RISCVBinaryWithV0;
}

defm vslideup : RVVSlide;
defm vslidedown : RVVSlide;

defm vslide1up : RISCVBinaryAAX;
defm vslide1down : RISCVBinaryAAX;
defm vfslide1up : RISCVBinaryAAX;
defm vfslide1down : RISCVBinaryAAX;

let IsFPIntrinsic = 1 in {
defm vfslide1up : RISCVBinaryAAX;
defm vfslide1down : RISCVBinaryAAX;
}

defm vrgather_vv : RISCVRGatherVV;
defm vrgather_vx : RISCVRGatherVX;
Expand All @@ -1571,12 +1580,14 @@ let TargetPrefix = "riscv" in {
defm vnclipu : RISCVSaturatingBinaryABShiftRoundingMode;
defm vnclip : RISCVSaturatingBinaryABShiftRoundingMode;

defm vmfeq : RISCVCompare;
defm vmfne : RISCVCompare;
defm vmflt : RISCVCompare;
defm vmfle : RISCVCompare;
defm vmfgt : RISCVCompare;
defm vmfge : RISCVCompare;
let IsFPIntrinsic = 1 in {
defm vmfeq : RISCVCompare;
defm vmfne : RISCVCompare;
defm vmflt : RISCVCompare;
defm vmfle : RISCVCompare;
defm vmfgt : RISCVCompare;
defm vmfge : RISCVCompare;
}

defm vredsum : RISCVReduction;
defm vredand : RISCVReduction;
Expand All @@ -1590,13 +1601,15 @@ let TargetPrefix = "riscv" in {
defm vwredsumu : RISCVReduction;
defm vwredsum : RISCVReduction;

defm vfredosum : RISCVReductionRoundingMode;
defm vfredusum : RISCVReductionRoundingMode;
defm vfredmin : RISCVReduction;
defm vfredmax : RISCVReduction;
let IsFPIntrinsic = 1 in {
defm vfredosum : RISCVReductionRoundingMode;
defm vfredusum : RISCVReductionRoundingMode;
defm vfredmin : RISCVReduction;
defm vfredmax : RISCVReduction;

defm vfwredusum : RISCVReductionRoundingMode;
defm vfwredosum : RISCVReductionRoundingMode;
defm vfwredusum : RISCVReductionRoundingMode;
defm vfwredosum : RISCVReductionRoundingMode;
}

def int_riscv_vmand: RISCVBinaryAAAUnMasked;
def int_riscv_vmnand: RISCVBinaryAAAUnMasked;
Expand All @@ -1615,31 +1628,33 @@ let TargetPrefix = "riscv" in {
defm vmsof : RISCVMaskedUnaryMOut;
defm vmsif : RISCVMaskedUnaryMOut;

defm vfcvt_xu_f_v : RISCVConversionRoundingMode;
defm vfcvt_x_f_v : RISCVConversionRoundingMode;
defm vfcvt_rtz_xu_f_v : RISCVConversion;
defm vfcvt_rtz_x_f_v : RISCVConversion;
defm vfcvt_f_xu_v : RISCVConversionRoundingMode;
defm vfcvt_f_x_v : RISCVConversionRoundingMode;

defm vfwcvt_f_xu_v : RISCVConversion;
defm vfwcvt_f_x_v : RISCVConversion;
defm vfwcvt_xu_f_v : RISCVConversionRoundingMode;
defm vfwcvt_x_f_v : RISCVConversionRoundingMode;
defm vfwcvt_rtz_xu_f_v : RISCVConversion;
defm vfwcvt_rtz_x_f_v : RISCVConversion;
defm vfwcvt_f_f_v : RISCVConversion;
defm vfwcvtbf16_f_f_v : RISCVConversion;

defm vfncvt_f_xu_w : RISCVConversionRoundingMode;
defm vfncvt_f_x_w : RISCVConversionRoundingMode;
defm vfncvt_xu_f_w : RISCVConversionRoundingMode;
defm vfncvt_x_f_w : RISCVConversionRoundingMode;
defm vfncvt_rtz_xu_f_w : RISCVConversion;
defm vfncvt_rtz_x_f_w : RISCVConversion;
defm vfncvt_f_f_w : RISCVConversionRoundingMode;
defm vfncvtbf16_f_f_w : RISCVConversionRoundingMode;
defm vfncvt_rod_f_f_w : RISCVConversion;
let IsFPIntrinsic = 1 in {
defm vfcvt_xu_f_v : RISCVConversionRoundingMode;
defm vfcvt_x_f_v : RISCVConversionRoundingMode;
defm vfcvt_rtz_xu_f_v : RISCVConversion;
defm vfcvt_rtz_x_f_v : RISCVConversion;
defm vfcvt_f_xu_v : RISCVConversionRoundingMode;
defm vfcvt_f_x_v : RISCVConversionRoundingMode;

defm vfwcvt_f_xu_v : RISCVConversion;
defm vfwcvt_f_x_v : RISCVConversion;
defm vfwcvt_xu_f_v : RISCVConversionRoundingMode;
defm vfwcvt_x_f_v : RISCVConversionRoundingMode;
defm vfwcvt_rtz_xu_f_v : RISCVConversion;
defm vfwcvt_rtz_x_f_v : RISCVConversion;
defm vfwcvt_f_f_v : RISCVConversion;
defm vfwcvtbf16_f_f_v : RISCVConversion;

defm vfncvt_f_xu_w : RISCVConversionRoundingMode;
defm vfncvt_f_x_w : RISCVConversionRoundingMode;
defm vfncvt_xu_f_w : RISCVConversionRoundingMode;
defm vfncvt_x_f_w : RISCVConversionRoundingMode;
defm vfncvt_rtz_xu_f_w : RISCVConversion;
defm vfncvt_rtz_x_f_w : RISCVConversion;
defm vfncvt_f_f_w : RISCVConversionRoundingMode;
defm vfncvtbf16_f_f_w : RISCVConversionRoundingMode;
defm vfncvt_rod_f_f_w : RISCVConversion;
}

// Output: (vector)
// Input: (passthru, mask type input, vl)
Expand Down
23 changes: 22 additions & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -723,8 +723,29 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();

if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID))
if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
if (II->hasScalarOperand() && !II->IsFPIntrinsic) {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();

auto OldScalar = MI.getOperand(II->ScalarOperand + 2).getReg();
// Legalize integer vx form intrinsic.
if (MRI.getType(OldScalar).isScalar()) {
if (MRI.getType(OldScalar).getSizeInBits() < sXLen.getSizeInBits()) {
Helper.Observer.changingInstr(MI);
Helper.widenScalarSrc(MI, sXLen, II->ScalarOperand + 2,
TargetOpcode::G_ANYEXT);
Helper.Observer.changedInstr(MI);
} else if (MRI.getType(OldScalar).getSizeInBits() >
sXLen.getSizeInBits()) {
// TODO: i64 in riscv32.
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Should we return false here so it fails?

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Addressed, added a return.

return false;
}
}
}
return true;
}

switch (IntrinsicID) {
default:
Expand Down
27 changes: 27 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Expand Up @@ -500,6 +500,33 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[1] = GPRValueMapping;
break;
}
case TargetOpcode::G_INTRINSIC: {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();

if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
unsigned ScalarIdx = -1;
if (II->hasScalarOperand()) {
ScalarIdx = II->ScalarOperand + 2;
}
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
const MachineOperand &MO = MI.getOperand(Idx);
if (!MO.isReg())
continue;
LLT Ty = MRI.getType(MO.getReg());
if (Ty.isVector()) {
OpdsMapping[Idx] =
getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue());
} else if (II->IsFPIntrinsic && ScalarIdx == Idx) {
// Chose the right FPR for scalar operand of RVV intrinsics.
OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits());
} else {
OpdsMapping[Idx] = GPRValueMapping;
}
}
}
break;
}
default:
// By default map all scalars to GPR.
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -642,6 +642,7 @@ struct RISCVVIntrinsicInfo {
unsigned IntrinsicID;
uint8_t ScalarOperand;
uint8_t VLOperand;
bool IsFPIntrinsic;
bool hasScalarOperand() const {
// 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
return ScalarOperand != 0xF;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -575,7 +575,7 @@ def RISCVVInversePseudosTable : GenericTable {
def RISCVVIntrinsicsTable : GenericTable {
let FilterClass = "RISCVVIntrinsic";
let CppTypeName = "RISCVVIntrinsicInfo";
let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand"];
let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand", "IsFPIntrinsic"];
let PrimaryKey = ["IntrinsicID"];
let PrimaryKeyName = "getRISCVVIntrinsicInfo";
}
Expand Down
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