[clang] VectorExprEvaluator::VisitCallExpr - add constant folding for X86 pslldqi/psrldqi intrinsics

clang/lib/AST/ExprConstant.cpp

@@ -11592,7 +11592,10 @@ static bool handleVectorElementCast(EvalInfo &Info, const FPOptions FPO,
       << SourceTy << DestTy;
   return false;
 }
-
+// i should emplement SLLDQ, SRLDQ shift (intrinsics) in constant expression
+// handling inside this function
+// avx2intrin.h -> _mm256_slli_si256
+// emmintrin.h -> _mm_slli_si128
 bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
   if (!IsConstantEvaluatedBuiltinCall(E))
     return ExprEvaluatorBaseTy::VisitCallExpr(E);
@@ -12034,6 +12037,46 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
 
     return Success(APValue(ResultElements.data(), ResultElements.size()), E);
   }
+  case X86::BI__builtin_ia32_pslldqi128_byteshift:
+  case X86::BI__builtin_ia32_psrldqi128_byteshift:
+  case X86::BI__builtin_ia32_pslldqi256_byteshift:
+  case X86::BI__builtin_ia32_psrldqi256_byteshift: {
+    APSInt Amt;
+    if (!EvaluateInteger(E->getArg(1), Amt, Info))
+      return false;
+    unsigned ShiftVal = (unsigned)Amt.getZExtValue() & 0xff;
+
+    APValue Vec;
+    if (!Evaluate(Vec, Info, E->getArg(0)) || !Vec.isVector())
+      return false;
+
+    unsigned NumElts = Vec.getVectorLength();
+    const unsigned LaneBytes = 16;
+    assert(NumElts % LaneBytes == 0);
+
+    SmallVector<APValue, 64> Result;
+    Result.resize(NumElts, APValue(0));
+
+    bool IsLeft =
+        (E->getBuiltinCallee() == X86::BI__builtin_ia32_pslldqi128_byteshift ||
+         E->getBuiltinCallee() == X86::BI__builtin_ia32_pslldqi256_byteshift);
+
+    if (ShiftVal >= LaneBytes)
+      return Success(APValue(Result.data(), Result.size()), E);
+
+    for (unsigned laneBase = 0; laneBase < NumElts; laneBase += LaneBytes) {
+      for (unsigned i = 0; i < LaneBytes; ++i) {
+        int src = IsLeft ? (i + ShiftVal) : (int)i - (int)ShiftVal;
+
+        if (src >= 0 && (unsigned)src < LaneBytes)
+          Result[laneBase + i] = Vec.getVectorElt(laneBase + (unsigned)src);
+        else
+          Result[laneBase + i] = APValue(0);
+      }
+    }
+
+    return Success(APValue(Result.data(), Result.size()), E);
+  }
   }
 }
 

clang/test/CodeGen/X86/avx2-builtins.c

@@ -1168,6 +1168,7 @@ __m256i test_mm256_slli_si256(__m256i a) {
   // CHECK: shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60>
   return _mm256_slli_si256(a, 3);
 }
+TEST_CONSTEXPR(match_v32qi(_mm256_slli_si256((__m256i)(__v32qi){1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116}, 5),0,0,0,0,0,1,2,3,4,5,6,7,8,9,10,11,0,0,0,0,0,101,102,103,104,105,106,107,108,109,110,111))
 
 __m128i test_mm_sllv_epi32(__m128i a, __m128i b) {
   // CHECK-LABEL: test_mm_sllv_epi32
@@ -1311,6 +1312,7 @@ __m256i test_mm256_srli_si256(__m256i a) {
   // CHECK: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50>
   return _mm256_srli_si256(a, 3);
 }
+TEST_CONSTEXPR(match_v32qi(_mm256_srli_si256((__m256i)(__v32qi){ 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116}, 5), 6,7,8,9,10,11,12,13,14,15,16,0,0,0,0,0, 106,107,108,109,110,111,112,113,114,115,116,0,0,0,0,0))
 
 __m128i test_mm_srlv_epi32(__m128i a, __m128i b) {
   // CHECK-LABEL: test_mm_srlv_epi32

clang/test/CodeGen/X86/sse2-builtins.c

@@ -1551,12 +1551,14 @@ __m128i test_mm_srli_si128(__m128i A) {
   // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
   return _mm_srli_si128(A, 5);
 }
+TEST_CONSTEXPR(match_v16qi(_mm_slli_si128((__m128i)(__v16qi){1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}, 3),0,0,0,1,2,3,4,5,6,7,8,9,10,11,12,13))
 
 __m128i test_mm_srli_si128_2(__m128i A) {
   // CHECK-LABEL: test_mm_srli_si128_2
   // ret <2 x i64> zeroinitializer
   return _mm_srli_si128(A, 17);
 }
+TEST_CONSTEXPR(match_v16qi(_mm_srli_si128((__m128i)(__v16qi){1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}, 3),4,5,6,7,8,9,10,11,12,13,14,15,16,0,0,0))
 
 void test_mm_store_pd(double* A, __m128d B) {
   // CHECK-LABEL: test_mm_store_pd