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[AArch64][SVE] Add PTEST_FIRST pseudo instruction #157489

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Merged
merged 1 commit into from
Sep 9, 2025
Merged

[AArch64][SVE] Add PTEST_FIRST pseudo instruction #157489

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10 changes: 7 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -22296,10 +22296,14 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
Op = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Op);
}

unsigned PTest = AArch64ISD::PTEST;
if (Cond == AArch64CC::ANY_ACTIVE)
PTest = AArch64ISD::PTEST_ANY;
else if (Cond == AArch64CC::FIRST_ACTIVE)
PTest = AArch64ISD::PTEST_FIRST;

// Set condition code (CC) flags.
SDValue Test = DAG.getNode(
Cond == AArch64CC::ANY_ACTIVE ? AArch64ISD::PTEST_ANY : AArch64ISD::PTEST,
DL, MVT::i32, Pg, Op);
SDValue Test = DAG.getNode(PTest, DL, MVT::i32, Pg, Op);

// Convert CC to integer based on requested condition.
// NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -1299,6 +1299,7 @@ bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
break;
case AArch64::PTEST_PP:
case AArch64::PTEST_PP_ANY:
case AArch64::PTEST_PP_FIRST:
SrcReg = MI.getOperand(0).getReg();
SrcReg2 = MI.getOperand(1).getReg();
if (MI.getOperand(2).getSubReg())
Expand Down Expand Up @@ -1691,7 +1692,8 @@ bool AArch64InstrInfo::optimizeCompareInstr(
}

if (CmpInstr.getOpcode() == AArch64::PTEST_PP ||
CmpInstr.getOpcode() == AArch64::PTEST_PP_ANY)
CmpInstr.getOpcode() == AArch64::PTEST_PP_ANY ||
CmpInstr.getOpcode() == AArch64::PTEST_PP_FIRST)
return optimizePTestInstr(&CmpInstr, SrcReg, SrcReg2, MRI);

if (SrcReg2 != 0)
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -412,6 +412,7 @@ def SDT_AArch64PTest : SDTypeProfile<1, 2, [
]>;
def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
def AArch64ptest_any : SDNode<"AArch64ISD::PTEST_ANY", SDT_AArch64PTest>;
def AArch64ptest_first : SDNode<"AArch64ISD::PTEST_FIRST", SDT_AArch64PTest>;

def SDT_AArch64DUP_PRED : SDTypeProfile<1, 3,
[SDTCisVec<0>, SDTCisSameAs<0, 3>, SDTCisVec<1>, SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0, 1>]>;
Expand Down Expand Up @@ -1071,7 +1072,7 @@ let Predicates = [HasSVE_or_SME] in {
defm BRKB_PPmP : sve_int_break_m<0b101, "brkb", int_aarch64_sve_brkb>;
defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs", null_frag>;

defm PTEST_PP : sve_int_ptest<0b010000, "ptest", AArch64ptest, AArch64ptest_any>;
defm PTEST_PP : sve_int_ptest<0b010000, "ptest", AArch64ptest, AArch64ptest_any, AArch64ptest_first>;
defm PFALSE : sve_int_pfalse<0b000000, "pfalse">;
defm PFIRST : sve_int_pfirst<0b00000, "pfirst", int_aarch64_sve_pfirst>;
defm PNEXT : sve_int_pnext<0b00110, "pnext", int_aarch64_sve_pnext>;
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6 changes: 5 additions & 1 deletion llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -893,13 +893,17 @@ class sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op>
}

multiclass sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op,
SDPatternOperator op_any> {
SDPatternOperator op_any, SDPatternOperator op_first> {
def NAME : sve_int_ptest<opc, asm, op>;

let hasNoSchedulingInfo = 1, isCompare = 1, Defs = [NZCV] in {
def _ANY : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
[(set NZCV, (op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>,
PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;

def _FIRST : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
[(set NZCV, (op_first (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>,
PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;
}
}

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