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[AArch64] Combine ADDS and SUBS nodes with the non-flag setting versions #157563

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Merged
merged 1 commit into from
Sep 13, 2025
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[AArch64] Combine ADDS and SUBS nodes with the non-flag setting versions #157563

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4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27179,6 +27179,10 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false))
return R;
return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
case AArch64ISD::ADDS:
return performFlagSettingCombine(N, DCI, ISD::ADD);
case AArch64ISD::SUBS:
return performFlagSettingCombine(N, DCI, ISD::SUB);
case AArch64ISD::BICi: {
APInt DemandedBits =
APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits());
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25 changes: 12 additions & 13 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -73,8 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: subs w8, w1, w8
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: cneg w0, w8, gt
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
%bext = sext i32 %b to i64
Expand Down Expand Up @@ -104,8 +104,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, gt
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -119,9 +119,8 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: subs w8, w8, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1, sxth
; CHECK-NEXT: cneg w0, w8, gt
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i16 %b to i64
Expand All @@ -135,8 +134,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, gt
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -150,8 +149,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, gt
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand All @@ -165,8 +164,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, gt
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/abds.ll
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Expand Up @@ -112,8 +112,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: subs w8, w0, w1, sxth
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
Expand Down
25 changes: 12 additions & 13 deletions llvm/test/CodeGen/AArch64/abdu-neg.ll
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Expand Up @@ -73,8 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: subs w8, w1, w8
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: cneg w0, w8, hi
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
%bext = zext i32 %b to i64
Expand Down Expand Up @@ -104,8 +104,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, hi
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i32 %b to i64
Expand All @@ -119,9 +119,8 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xffff
; CHECK-NEXT: subs w8, w8, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: subs w8, w0, w1, uxth
; CHECK-NEXT: cneg w0, w8, hi
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i16 %b to i64
Expand All @@ -135,8 +134,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, hi
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i32 %b to i64
Expand All @@ -150,8 +149,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, hi
; CHECK-NEXT: ret
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
Expand All @@ -165,8 +164,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, hi
; CHECK-NEXT: ret
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/abdu.ll
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Expand Up @@ -112,8 +112,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xffff
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: subs w8, w0, w1, uxth
; CHECK-NEXT: cneg w0, w8, ls
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AArch64/adds_cmn.ll
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Expand Up @@ -4,10 +4,8 @@
define { i32, i32 } @adds_cmn(i32 noundef %x, i32 noundef %y) {
; CHECK-LABEL: adds_cmn:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, w1
; CHECK-NEXT: add w1, w0, w1
; CHECK-NEXT: cset w8, lo
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: adds w1, w0, w1
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
entry:
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %y)
Expand Down