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[DAGCombiner] Fix type check in visitSRA: use VT for SIGN_EXTEND and TruncVT for TRUNCATE #157580

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[DAGCombiner] Fix type check in visitSRA: use VT for SIGN_EXTEND and TruncVT for TRUNCATE #157580

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1c87083
[DAGCombiner] Fix type check in visitSRA: use VT for SIGN_EXTEND and …
Sep 8, 2025
b74b4b0
Merge branch 'main' into fix-sra-legal-check
StephenYoung2754 Sep 10, 2025
f2231b6
Merge branch 'main' into fix-sra-legal-check
StephenYoung2754 Sep 10, 2025
2ce18c9
Merge branch 'main' into fix-sra-legal-check
StephenYoung2754 Sep 11, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10888,8 +10888,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// on that type, and the truncate to that type is both legal and free,
// perform the transform.
if ((ShiftAmt > 0) &&
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, VT) &&
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, TruncVT) &&
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? This changes nothing.

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Thank you for pointing this out. You’re right — I accidentally submitted a wrong edit which didn’t fix the issue.
I’ve updated the patch so that SIGN_EXTEND is checked against VT (the result type) and TRUNCATE against TruncVT (the truncated type).
Please take another look.

TLI.isTruncateFree(VT, TruncVT)) {
SDValue Amt = DAG.getShiftAmountConstant(ShiftAmt, VT, DL);
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
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