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[ROCDL] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 #157748

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[ROCDL] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 #157748

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49f6936
Added Intrinsics for smed, umed, to support ISA instructions from ROCDL
keshavvinayak01 Sep 9, 2025
6cb12ec
Tested succesful rocdl -> llvm rewrites for smed,umed,fmed
keshavvinayak01 Sep 10, 2025
8267484
Added smed3, umed3 amdgcn.& -> asm lits; Added rocdl -> llvm lowering…
keshavvinayak01 Sep 11, 2025
5f8f446
Merge branch 'main' into users/keshavvinayak01/smed-umed-extensions
keshavvinayak01 Sep 11, 2025
49a0f2b
Removed smed3/umed3 intrinsics; only keeping rocdl.fmed3.
keshavvinayak01 Sep 15, 2025
86441ab
Added back old InstrInfo/GISel for smed/umed
keshavvinayak01 Sep 15, 2025
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32 changes: 32 additions & 0 deletions mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1291,6 +1291,38 @@ def ROCDL_CvtScaleF32PkFp4F32Op :
}];
}

//===----------------------------------------------------------------------===//
// MED3 operations
//===----------------------------------------------------------------------===//

def ROCDL_Med3F16Op : ROCDL_ConcreteNonMemIntrOp<"med3.f16", [Pure], 1>,
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@krzysz00 krzysz00 Sep 17, 2025

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Strong reject of having two ops that differ only in type. Please make this one operation with a variadic type. There should be existing examples.

Arguments<(ins F16:$src0,
F16:$src1,
F16:$src2)> {
let results = (outs F16:$res);
let summary = "Median of three half-precision float values";
let assemblyFormat = [{
$src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res)
}];
string llvmBuilder = [{
$res = createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_fmed3, {$src0, $src1, $src2}, {moduleTranslation.convertType(op.getSrc0().getType())});
}];
}

def ROCDL_Med3F32Op : ROCDL_ConcreteNonMemIntrOp<"med3.f32", [Pure], 1>,
Arguments<(ins F32:$src0,
F32:$src1,
F32:$src2)> {
let results = (outs F32:$res);
let summary = "Median of three single-precision float values";
let assemblyFormat = [{
$src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res)
}];
string llvmBuilder = [{
$res = createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_fmed3, {$src0, $src1, $src2}, {moduleTranslation.convertType(op.getSrc0().getType())});
}];
}

//===----------------------------------------------------------------------===//
// ROCDL target attribute.
//===----------------------------------------------------------------------===//
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14 changes: 14 additions & 0 deletions mlir/test/Target/LLVMIR/rocdl.mlir
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Expand Up @@ -1298,6 +1298,20 @@ llvm.func @rocdl_last_use(%ptr: !llvm.ptr<1>) -> i32 {
llvm.return %ret : i32
}

llvm.func @test_med3_f16(%arg0: f16, %arg1: f16, %arg2: f16) -> f16 {
// CHECK-LABEL: define half @test_med3_f16(half %0, half %1, half %2)
%0 = rocdl.med3.f16 %arg0, %arg1, %arg2 : (f16, f16, f16) -> f16
llvm.return %0 : f16
// CHECK: call half @llvm.amdgcn.fmed3.f16(half %0, half %1, half %2)
}

llvm.func @test_med3_f32(%arg0: f32, %arg1: f32, %arg2: f32) -> f32 {
// CHECK-LABEL: define float @test_med3_f32(float %0, float %1, float %2)
%0 = rocdl.med3.f32 %arg0, %arg1, %arg2 : (f32, f32, f32) -> f32
llvm.return %0 : f32
// CHECK: call float @llvm.amdgcn.fmed3.f32(float %0, float %1, float %2)
}

// CHECK-DAG: attributes #[[$KERNEL_ATTRS]] = { "amdgpu-flat-work-group-size"="1,256" "uniform-work-group-size"="true" }
// CHECK-DAG: attributes #[[$KERNEL_WORKGROUP_ATTRS]] = { "amdgpu-flat-work-group-size"="1,1024"
// CHECK-DAG: attributes #[[$KNOWN_BLOCK_SIZE_ATTRS]] = { "amdgpu-flat-work-group-size"="128,128"
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