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AMDGPU: Remove most manual AVLdSt decoder code #157861

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Sep 10, 2025
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AMDGPU: Remove most manual AVLdSt decoder code #157861

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42 changes: 0 additions & 42 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -368,51 +368,9 @@ static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
}

static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
const MCRegisterInfo *MRI) {
if (OpIdx < 0)
return false;

const MCOperand &Op = Inst.getOperand(OpIdx);
if (!Op.isReg())
return false;

MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg();
return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
}

static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, unsigned Opw,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
if (!DAsm->isGFX90A()) {
Imm &= 511;
} else {
// If atomic has both vdata and vdst their register classes are tied.
// The bit is decoded along with the vdst, first operand. We need to
// change register class to AGPR if vdst was AGPR.
// If a DS instruction has both data0 and data1 their register classes
// are also tied.
unsigned Opc = Inst.getOpcode();
uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
? AMDGPU::OpName::data0
: AMDGPU::OpName::vdata;
const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataName);
if ((int)Inst.getNumOperands() == DataIdx) {
int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (IsAGPROperand(Inst, DstIdx, MRI))
Imm |= 512;
}

if (TSFlags & SIInstrFlags::DS) {
int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
if ((int)Inst.getNumOperands() == Data2Idx &&
IsAGPROperand(Inst, DataIdx, MRI))
Imm |= 512;
}
}
return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
}

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