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The latest SP changes updated it to use OP_SEL[0:3] instead of OP_SEL[0:2].

Fixes SWDEV-554472.

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llvmbot commented Sep 10, 2025

@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

Changes

The latest SP changes updated it to use OP_SEL[0:3] instead of OP_SEL[0:2].

Fixes SWDEV-554472.


Full diff: https://github.com/llvm/llvm-project/pull/157900.diff

2 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+1-1)
  • (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s (+2-2)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index aa5dae09ca185..7b877a4f74373 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1353,7 +1353,7 @@ def MatrixAReuse : NamedBitOperand<"matrix_a_reuse">;
 def MatrixBReuse : NamedBitOperand<"matrix_b_reuse">;
 
 def ScaleSel : NamedIntOperand<"scale_sel"> {
-  let Validator = "isUInt<3>";
+  let Validator = "isUInt<4>";
 }
 
 class KImmFPOperand<ValueType vt> : ImmOperand<vt> {
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
index e87943224e8f5..cce8e1ef24f5f 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
@@ -277,9 +277,9 @@ v_cvt_sr_fp8_f16 v1, v2, v3 mul:2
 // GFX125X-ERR-NEXT:{{^}}v_cvt_sr_fp8_f16 v1, v2, v3 mul:2
 // GFX125X-ERR-NEXT:{{^}}                            ^
 
-v_cvt_scale_pk8_f32_fp8 v[10:17], v[20:21], v8 scale_sel:8
+v_cvt_scale_pk8_f32_fp8 v[10:17], v[20:21], v8 scale_sel:16
 // GFX125X-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid scale_sel value.
-// GFX125X-ERR-NEXT:{{^}}v_cvt_scale_pk8_f32_fp8 v[10:17], v[20:21], v8 scale_sel:8
+// GFX125X-ERR-NEXT:{{^}}v_cvt_scale_pk8_f32_fp8 v[10:17], v[20:21], v8 scale_sel:16
 // GFX125X-ERR-NEXT:{{^}}                                               ^
 
 v_cvt_sr_bf8_f16 v1, v2, v3 byte_sel:4

@shiltian shiltian marked this pull request as draft September 10, 2025 17:09
The latest SP changes updated it to use `OP_SEL[0:3]` instead of `OP_SEL[0:2]`.

Fixes SWDEV-554472.
@shiltian shiltian force-pushed the users/shiltian/4-bit-scale_sel branch from a0ec131 to d7ea946 Compare September 10, 2025 17:15
@shiltian shiltian marked this pull request as ready for review September 10, 2025 17:15
@llvmbot llvmbot added clang Clang issues not falling into any other category clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir labels Sep 10, 2025
@rampitec
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SP3 uses 3 bits. I would hold this before SP3 is changed.

@shiltian
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@rampitec SP3 has been updated.

@shiltian shiltian merged commit 158eeb3 into main Sep 16, 2025
14 checks passed
@shiltian shiltian deleted the users/shiltian/4-bit-scale_sel branch September 16, 2025 19:36
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