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AMDGPU: Report unaligned scratch access as fast if supported by tgt #158036

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merged 5 commits into from
Sep 15, 2025
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AMDGPU: Report unaligned scratch access as fast if supported by tgt #158036

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70332f2
AMDGPU: Report unaligned scratch access as fast if supported by tgt
macurtis-amd Jun 27, 2025
53f8dd4
fixup! AMDGPU: Report unaligned scratch access as fast if supported b…
macurtis-amd Sep 12, 2025
16136d5
fixup! AMDGPU: Report unaligned scratch access as fast if supported b…
macurtis-amd Sep 12, 2025
d6db617
fixup! AMDGPU: Report unaligned scratch access as fast if supported b…
macurtis-amd Sep 12, 2025
4f8e69e
fixup! AMDGPU: Report unaligned scratch access as fast if supported b…
macurtis-amd Sep 12, 2025
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8 changes: 7 additions & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2098,10 +2098,16 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
AddrSpace == AMDGPUAS::FLAT_ADDRESS) {
bool AlignedBy4 = Alignment >= Align(4);
if (Subtarget->hasUnalignedScratchAccessEnabled()) {
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Can you change the title to describe this is changing reporting of fast unaligned access, and mention the consequence in the longer description

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Updated title and description.

if (IsFast)
*IsFast = AlignedBy4 ? Size : 1;
return true;
}

if (IsFast)
*IsFast = AlignedBy4;

return AlignedBy4 || Subtarget->hasUnalignedScratchAccessEnabled();
return AlignedBy4;
}

// So long as they are correct, wide global memory operations perform better
Expand Down
16 changes: 9 additions & 7 deletions llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
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Expand Up @@ -7,23 +7,25 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; MUBUF-LABEL: memcpy_fixed_align:
; MUBUF: ; %bb.0:
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MUBUF-NEXT: global_load_dwordx2 v[11:12], v[1:2], off offset:32
; MUBUF-NEXT: global_load_dwordx4 v[3:6], v[1:2], off
; MUBUF-NEXT: global_load_dwordx4 v[7:10], v[1:2], off offset:16
; MUBUF-NEXT: global_load_dwordx4 v[11:14], v[1:2], off offset:24
; MUBUF-NEXT: s_lshr_b32 s4, s32, 6
; MUBUF-NEXT: s_waitcnt vmcnt(2)
; MUBUF-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:32
; MUBUF-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:36
; MUBUF-NEXT: s_waitcnt vmcnt(3)
; MUBUF-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:12
; MUBUF-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:8
; MUBUF-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:4
; MUBUF-NEXT: buffer_store_dword v3, off, s[0:3], s32
; MUBUF-NEXT: s_waitcnt vmcnt(6)
; MUBUF-NEXT: s_waitcnt vmcnt(5)
; MUBUF-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:28
; MUBUF-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:24
; MUBUF-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:20
; MUBUF-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:16
; MUBUF-NEXT: s_waitcnt vmcnt(8)
; MUBUF-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:36
; MUBUF-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:32
; MUBUF-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:28
; MUBUF-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:24
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; use s4
; MUBUF-NEXT: ;;#ASMEND
Expand All @@ -35,14 +37,14 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: global_load_dwordx4 v[3:6], v[1:2], off
; FLATSCR-NEXT: global_load_dwordx4 v[7:10], v[1:2], off offset:16
; FLATSCR-NEXT: global_load_dwordx2 v[11:12], v[1:2], off offset:32
; FLATSCR-NEXT: global_load_dwordx4 v[11:14], v[1:2], off offset:24
; FLATSCR-NEXT: s_mov_b32 s0, s32
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
; FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s32
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
; FLATSCR-NEXT: scratch_store_dwordx4 off, v[7:10], s32 offset:16
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[11:12], s32 offset:32
; FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s32 offset:24
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; use s0
; FLATSCR-NEXT: ;;#ASMEND
Expand Down
152 changes: 74 additions & 78 deletions llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
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Expand Up @@ -12,21 +12,19 @@ define amdgpu_kernel void @memcpy_p0_p0_minsize(ptr %dest, ptr readonly %src) #0
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v12, s3
; CHECK-NEXT: v_mov_b32_e32 v11, s2
; CHECK-NEXT: flat_load_ubyte v13, v[11:12] offset:46
; CHECK-NEXT: flat_load_ushort v14, v[11:12] offset:44
; CHECK-NEXT: flat_load_dwordx3 v[8:10], v[11:12] offset:32
; CHECK-NEXT: flat_load_dwordx4 v[0:3], v[11:12] offset:16
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[11:12]
; CHECK-NEXT: v_mov_b32_e32 v12, s1
; CHECK-NEXT: v_mov_b32_e32 v11, s0
; CHECK-NEXT: v_mov_b32_e32 v9, s3
; CHECK-NEXT: v_mov_b32_e32 v8, s2
; CHECK-NEXT: flat_load_dwordx2 v[10:11], v[8:9] offset:32
; CHECK-NEXT: flat_load_dwordx2 v[12:13], v[8:9] offset:39
; CHECK-NEXT: flat_load_dwordx4 v[0:3], v[8:9]
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[8:9] offset:16
; CHECK-NEXT: v_mov_b32_e32 v9, s1
; CHECK-NEXT: v_mov_b32_e32 v8, s0
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_store_byte v[11:12], v13 offset:46
; CHECK-NEXT: flat_store_short v[11:12], v14 offset:44
; CHECK-NEXT: flat_store_dwordx3 v[11:12], v[8:10] offset:32
; CHECK-NEXT: flat_store_dwordx4 v[11:12], v[0:3] offset:16
; CHECK-NEXT: flat_store_dwordx4 v[11:12], v[4:7]
; CHECK-NEXT: flat_store_dwordx2 v[8:9], v[10:11] offset:32
; CHECK-NEXT: flat_store_dwordx2 v[8:9], v[12:13] offset:39
; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[4:7] offset:16
; CHECK-NEXT: s_endpgm
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 47, i1 false)
Expand Down Expand Up @@ -173,33 +171,33 @@ define amdgpu_kernel void @memcpy_p0_p5_minsize(ptr %generic, ptr addrspace(5) %
; CHECK-NEXT: v_mov_b32_e32 v26, s0
; CHECK-NEXT: buffer_load_dword v3, v26, s[20:23], 0 offen offset:124
; CHECK-NEXT: buffer_load_dword v2, v26, s[20:23], 0 offen offset:120
; CHECK-NEXT: buffer_load_dword v5, v26, s[20:23], 0 offen offset:100
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:108
; CHECK-NEXT: buffer_load_dword v1, v26, s[20:23], 0 offen offset:116
; CHECK-NEXT: buffer_load_dword v0, v26, s[20:23], 0 offen offset:112
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:108
; CHECK-NEXT: buffer_load_dword v6, v26, s[20:23], 0 offen offset:104
; CHECK-NEXT: buffer_load_dword v5, v26, s[20:23], 0 offen offset:100
; CHECK-NEXT: buffer_load_dword v4, v26, s[20:23], 0 offen offset:96
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: buffer_load_dword v8, v26, s[20:23], 0 offen offset:32
; CHECK-NEXT: buffer_load_dword v9, v26, s[20:23], 0 offen offset:36
; CHECK-NEXT: buffer_load_dword v10, v26, s[20:23], 0 offen offset:40
; CHECK-NEXT: buffer_load_dword v11, v26, s[20:23], 0 offen offset:44
; CHECK-NEXT: buffer_load_dword v12, v26, s[20:23], 0 offen offset:48
; CHECK-NEXT: buffer_load_dword v13, v26, s[20:23], 0 offen offset:52
; CHECK-NEXT: buffer_load_dword v14, v26, s[20:23], 0 offen offset:56
; CHECK-NEXT: buffer_load_dword v15, v26, s[20:23], 0 offen offset:60
; CHECK-NEXT: buffer_load_dword v17, v26, s[20:23], 0 offen offset:68
; CHECK-NEXT: buffer_load_dword v19, v26, s[20:23], 0 offen offset:76
; CHECK-NEXT: buffer_load_dword v21, v26, s[20:23], 0 offen offset:84
; CHECK-NEXT: buffer_load_dword v23, v26, s[20:23], 0 offen offset:92
; CHECK-NEXT: buffer_load_dword v22, v26, s[20:23], 0 offen offset:88
; CHECK-NEXT: buffer_load_dword v20, v26, s[20:23], 0 offen offset:80
; CHECK-NEXT: buffer_load_dword v18, v26, s[20:23], 0 offen offset:72
; CHECK-NEXT: buffer_load_dword v16, v26, s[20:23], 0 offen offset:64
; CHECK-NEXT: buffer_load_dword v11, v26, s[20:23], 0 offen offset:92
; CHECK-NEXT: buffer_load_dword v10, v26, s[20:23], 0 offen offset:88
; CHECK-NEXT: buffer_load_dword v9, v26, s[20:23], 0 offen offset:84
; CHECK-NEXT: buffer_load_dword v8, v26, s[20:23], 0 offen offset:80
; CHECK-NEXT: buffer_load_dword v15, v26, s[20:23], 0 offen offset:76
; CHECK-NEXT: buffer_load_dword v14, v26, s[20:23], 0 offen offset:72
; CHECK-NEXT: buffer_load_dword v13, v26, s[20:23], 0 offen offset:68
; CHECK-NEXT: buffer_load_dword v12, v26, s[20:23], 0 offen offset:64
; CHECK-NEXT: buffer_load_dword v16, v26, s[20:23], 0 offen offset:32
; CHECK-NEXT: buffer_load_dword v17, v26, s[20:23], 0 offen offset:36
; CHECK-NEXT: buffer_load_dword v18, v26, s[20:23], 0 offen offset:40
; CHECK-NEXT: buffer_load_dword v19, v26, s[20:23], 0 offen offset:44
; CHECK-NEXT: buffer_load_dword v20, v26, s[20:23], 0 offen offset:48
; CHECK-NEXT: buffer_load_dword v21, v26, s[20:23], 0 offen offset:52
; CHECK-NEXT: buffer_load_dword v22, v26, s[20:23], 0 offen offset:56
; CHECK-NEXT: buffer_load_dword v23, v26, s[20:23], 0 offen offset:60
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v25, s1
; CHECK-NEXT: v_mov_b32_e32 v24, s0
; CHECK-NEXT: s_waitcnt vmcnt(18)
; CHECK-NEXT: s_waitcnt vmcnt(20)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[0:3] offset:112
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[4:7] offset:96
Expand All @@ -213,10 +211,10 @@ define amdgpu_kernel void @memcpy_p0_p5_minsize(ptr %generic, ptr addrspace(5) %
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:28
; CHECK-NEXT: buffer_load_dword v3, v26, s[20:23], 0 offen offset:12
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[20:23] offset:80
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[16:19] offset:64
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[12:15] offset:48
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[8:11] offset:32
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[8:11] offset:80
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[12:15] offset:64
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[20:23] offset:48
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[16:19] offset:32
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[4:7] offset:16
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
Expand Down Expand Up @@ -281,8 +279,8 @@ define amdgpu_kernel void @memcpy_p0_p3_minsize(ptr %generic) #0 {
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[8:11] offset:32
; CHECK-NEXT: ds_read2_b64 v[0:3], v16 offset0:8 offset1:9
; CHECK-NEXT: ds_read2_b64 v[4:7], v16 offset0:10 offset1:11
; CHECK-NEXT: ds_read2_b64 v[8:11], v16 offset0:12 offset1:13
; CHECK-NEXT: ds_read2_b64 v[16:19], v16 offset0:14 offset1:15
; CHECK-NEXT: ds_read_b128 v[8:11], v16 offset:96
; CHECK-NEXT: ds_read_b128 v[16:19], v16 offset:112
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[12:15] offset:48
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[0:3] offset:64
Expand All @@ -302,21 +300,19 @@ define amdgpu_kernel void @memcpy_p0_p0_optsize(ptr %dest, ptr %src) #1 {
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v12, s3
; CHECK-NEXT: v_mov_b32_e32 v11, s2
; CHECK-NEXT: flat_load_ubyte v13, v[11:12] offset:46
; CHECK-NEXT: flat_load_ushort v14, v[11:12] offset:44
; CHECK-NEXT: flat_load_dwordx3 v[8:10], v[11:12] offset:32
; CHECK-NEXT: flat_load_dwordx4 v[0:3], v[11:12] offset:16
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[11:12]
; CHECK-NEXT: v_mov_b32_e32 v12, s1
; CHECK-NEXT: v_mov_b32_e32 v11, s0
; CHECK-NEXT: v_mov_b32_e32 v9, s3
; CHECK-NEXT: v_mov_b32_e32 v8, s2
; CHECK-NEXT: flat_load_dwordx2 v[10:11], v[8:9] offset:32
; CHECK-NEXT: flat_load_dwordx2 v[12:13], v[8:9] offset:39
; CHECK-NEXT: flat_load_dwordx4 v[0:3], v[8:9]
; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[8:9] offset:16
; CHECK-NEXT: v_mov_b32_e32 v9, s1
; CHECK-NEXT: v_mov_b32_e32 v8, s0
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_store_byte v[11:12], v13 offset:46
; CHECK-NEXT: flat_store_short v[11:12], v14 offset:44
; CHECK-NEXT: flat_store_dwordx3 v[11:12], v[8:10] offset:32
; CHECK-NEXT: flat_store_dwordx4 v[11:12], v[0:3] offset:16
; CHECK-NEXT: flat_store_dwordx4 v[11:12], v[4:7]
; CHECK-NEXT: flat_store_dwordx2 v[8:9], v[10:11] offset:32
; CHECK-NEXT: flat_store_dwordx2 v[8:9], v[12:13] offset:39
; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[4:7] offset:16
; CHECK-NEXT: s_endpgm
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 47, i1 false)
Expand Down Expand Up @@ -463,33 +459,33 @@ define amdgpu_kernel void @memcpy_p0_p5_optsize(ptr %generic, ptr addrspace(5) %
; CHECK-NEXT: v_mov_b32_e32 v26, s0
; CHECK-NEXT: buffer_load_dword v3, v26, s[20:23], 0 offen offset:124
; CHECK-NEXT: buffer_load_dword v2, v26, s[20:23], 0 offen offset:120
; CHECK-NEXT: buffer_load_dword v5, v26, s[20:23], 0 offen offset:100
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:108
; CHECK-NEXT: buffer_load_dword v1, v26, s[20:23], 0 offen offset:116
; CHECK-NEXT: buffer_load_dword v0, v26, s[20:23], 0 offen offset:112
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:108
; CHECK-NEXT: buffer_load_dword v6, v26, s[20:23], 0 offen offset:104
; CHECK-NEXT: buffer_load_dword v5, v26, s[20:23], 0 offen offset:100
; CHECK-NEXT: buffer_load_dword v4, v26, s[20:23], 0 offen offset:96
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: buffer_load_dword v8, v26, s[20:23], 0 offen offset:32
; CHECK-NEXT: buffer_load_dword v9, v26, s[20:23], 0 offen offset:36
; CHECK-NEXT: buffer_load_dword v10, v26, s[20:23], 0 offen offset:40
; CHECK-NEXT: buffer_load_dword v11, v26, s[20:23], 0 offen offset:44
; CHECK-NEXT: buffer_load_dword v12, v26, s[20:23], 0 offen offset:48
; CHECK-NEXT: buffer_load_dword v13, v26, s[20:23], 0 offen offset:52
; CHECK-NEXT: buffer_load_dword v14, v26, s[20:23], 0 offen offset:56
; CHECK-NEXT: buffer_load_dword v15, v26, s[20:23], 0 offen offset:60
; CHECK-NEXT: buffer_load_dword v17, v26, s[20:23], 0 offen offset:68
; CHECK-NEXT: buffer_load_dword v19, v26, s[20:23], 0 offen offset:76
; CHECK-NEXT: buffer_load_dword v21, v26, s[20:23], 0 offen offset:84
; CHECK-NEXT: buffer_load_dword v23, v26, s[20:23], 0 offen offset:92
; CHECK-NEXT: buffer_load_dword v22, v26, s[20:23], 0 offen offset:88
; CHECK-NEXT: buffer_load_dword v20, v26, s[20:23], 0 offen offset:80
; CHECK-NEXT: buffer_load_dword v18, v26, s[20:23], 0 offen offset:72
; CHECK-NEXT: buffer_load_dword v16, v26, s[20:23], 0 offen offset:64
; CHECK-NEXT: buffer_load_dword v11, v26, s[20:23], 0 offen offset:92
; CHECK-NEXT: buffer_load_dword v10, v26, s[20:23], 0 offen offset:88
; CHECK-NEXT: buffer_load_dword v9, v26, s[20:23], 0 offen offset:84
; CHECK-NEXT: buffer_load_dword v8, v26, s[20:23], 0 offen offset:80
; CHECK-NEXT: buffer_load_dword v15, v26, s[20:23], 0 offen offset:76
; CHECK-NEXT: buffer_load_dword v14, v26, s[20:23], 0 offen offset:72
; CHECK-NEXT: buffer_load_dword v13, v26, s[20:23], 0 offen offset:68
; CHECK-NEXT: buffer_load_dword v12, v26, s[20:23], 0 offen offset:64
; CHECK-NEXT: buffer_load_dword v16, v26, s[20:23], 0 offen offset:32
; CHECK-NEXT: buffer_load_dword v17, v26, s[20:23], 0 offen offset:36
; CHECK-NEXT: buffer_load_dword v18, v26, s[20:23], 0 offen offset:40
; CHECK-NEXT: buffer_load_dword v19, v26, s[20:23], 0 offen offset:44
; CHECK-NEXT: buffer_load_dword v20, v26, s[20:23], 0 offen offset:48
; CHECK-NEXT: buffer_load_dword v21, v26, s[20:23], 0 offen offset:52
; CHECK-NEXT: buffer_load_dword v22, v26, s[20:23], 0 offen offset:56
; CHECK-NEXT: buffer_load_dword v23, v26, s[20:23], 0 offen offset:60
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v25, s1
; CHECK-NEXT: v_mov_b32_e32 v24, s0
; CHECK-NEXT: s_waitcnt vmcnt(18)
; CHECK-NEXT: s_waitcnt vmcnt(20)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[0:3] offset:112
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[4:7] offset:96
Expand All @@ -503,10 +499,10 @@ define amdgpu_kernel void @memcpy_p0_p5_optsize(ptr %generic, ptr addrspace(5) %
; CHECK-NEXT: buffer_load_dword v7, v26, s[20:23], 0 offen offset:28
; CHECK-NEXT: buffer_load_dword v3, v26, s[20:23], 0 offen offset:12
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[20:23] offset:80
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[16:19] offset:64
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[12:15] offset:48
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[8:11] offset:32
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[8:11] offset:80
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[12:15] offset:64
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[20:23] offset:48
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[16:19] offset:32
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[4:7] offset:16
; CHECK-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
Expand Down Expand Up @@ -571,8 +567,8 @@ define amdgpu_kernel void @memcpy_p0_p3_optsize(ptr %generic) #1 {
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[8:11] offset:32
; CHECK-NEXT: ds_read2_b64 v[0:3], v16 offset0:8 offset1:9
; CHECK-NEXT: ds_read2_b64 v[4:7], v16 offset0:10 offset1:11
; CHECK-NEXT: ds_read2_b64 v[8:11], v16 offset0:12 offset1:13
; CHECK-NEXT: ds_read2_b64 v[16:19], v16 offset0:14 offset1:15
; CHECK-NEXT: ds_read_b128 v[8:11], v16 offset:96
; CHECK-NEXT: ds_read_b128 v[16:19], v16 offset:112
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[12:15] offset:48
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[0:3] offset:64
Expand Down
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