Skip to content

[NFC][DecoderEmitter] Predicate generation code cleanup #158140

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 6 commits into from
Sep 16, 2025
Merged

[NFC][DecoderEmitter] Predicate generation code cleanup #158140

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
ae4f936
[NFC][DecoderEmitter] Predicate generation code cleanup
jurahul Sep 11, 2025
62a1ea2
Review feedback
jurahul Sep 14, 2025
29a6875
Drop outer ()
jurahul Sep 15, 2025
139f7f2
Clang-format fixes
jurahul Sep 15, 2025
328f1f3
Review feedback
jurahul Sep 16, 2025
2798560
One more missing ;
jurahul Sep 16, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 5 additions & 5 deletions llvm/test/TableGen/AsmPredicateCombining.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -63,19 +63,19 @@ def AsmPred4 : Predicate<"Pred4">, AssemblerPredicate<(all_of AsmCond4, (not (an
// MATCHER-NEXT: Features.set(Feature_AsmPred4Bit);

def insn1 : TestInsn<1, [AsmPred1]>;
// DISASS: return (Bits[arch::AsmCond1]);
// DISASS: return FB[arch::AsmCond1];

def insn2 : TestInsn<2, [AsmPred2]>;
// DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
// DISASS: return FB[arch::AsmCond2a] && FB[arch::AsmCond2b];

def insn3 : TestInsn<3, [AsmPred3]>;
// DISASS: return (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])
// DISASS: return FB[arch::AsmCond3a] || FB[arch::AsmCond3b];

def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]))
// DISASS: return FB[arch::AsmCond1] && (FB[arch::AsmCond2a] && FB[arch::AsmCond2b]);

def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
// DISASS: return FB[arch::AsmCond1] && (FB[arch::AsmCond3a] || FB[arch::AsmCond3b]);

def insn6 : TestInsn<6, []>;
def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/AsmPredicateCondsEmission.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,4 +29,4 @@ def foo : Instruction {
let Predicates = [Pred1, Pred2];
}

// CHECK: return (Bits[arch::AssemblerCondition2]);
// CHECK: return FB[arch::AssemblerCondition2];
15 changes: 9 additions & 6 deletions llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -190,8 +190,9 @@ void SubtargetFeatureInfo::emitMCPredicateCheck(
bool ParenIfBinOp = range_size(MCPredicates) > 1;
for (const Record *R : MCPredicates) {
OS << LS;
emitFeaturesAux(TargetName, *R->getValueAsDag("AssemblerCondDag"),
ParenIfBinOp, OS);
if (emitFeaturesAux(TargetName, *R->getValueAsDag("AssemblerCondDag"),
ParenIfBinOp, OS))
PrintFatalError(R, "Invalid AssemblerCondDag!");
}
}

Expand All @@ -206,12 +207,14 @@ void SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
OS << "const ";
OS << "{\n";
OS << " FeatureBitset Features;\n";
for (const auto &SF : SubtargetFeatures) {
const SubtargetFeatureInfo &SFI = SF.second;
for (const SubtargetFeatureInfo &SFI : make_second_range(SubtargetFeatures)) {
const Record *Def = SFI.TheDef;

OS << " if (";
emitFeaturesAux(TargetName, *SFI.TheDef->getValueAsDag("AssemblerCondDag"),
/*ParenIfBinOp=*/false, OS);
if (emitFeaturesAux(TargetName, *Def->getValueAsDag("AssemblerCondDag"),
/*ParenIfBinOp=*/false, OS))
PrintFatalError(Def, "Invalid AssemblerCondDag!");

OS << ")\n";
OS << " Features.set(" << SFI.getEnumBitName() << ");\n";
}
Expand Down
59 changes: 16 additions & 43 deletions llvm/utils/TableGen/DecoderEmitter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#include "Common/CodeGenTarget.h"
#include "Common/InfoByHwMode.h"
#include "Common/InstructionEncoding.h"
#include "Common/SubtargetFeatureInfo.h"
#include "Common/VarLenCodeEmitterGen.h"
#include "TableGenBackends.h"
#include "llvm/ADT/APInt.h"
Expand Down Expand Up @@ -519,8 +520,6 @@ class DecoderTableBuilder {

bool emitPredicateMatch(raw_ostream &OS, unsigned EncodingID) const;

bool doesOpcodeNeedPredicate(unsigned EncodingID) const;

void emitPredicateTableEntry(unsigned EncodingID) const;

void emitSoftFailTableEntry(unsigned EncodingID) const;
Expand Down Expand Up @@ -839,12 +838,12 @@ void DecoderEmitter::emitPredicateFunction(formatted_raw_ostream &OS,
// The predicate function is just a big switch statement based on the
// input predicate index.
OS << "static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset "
"&Bits) {\n";
"&FB) {\n";
OS << " switch (Idx) {\n";
OS << " default: llvm_unreachable(\"Invalid index!\");\n";
for (const auto &[Index, Predicate] : enumerate(Predicates)) {
OS << " case " << Index << ":\n";
OS << " return (" << Predicate << ");\n";
OS << " return " << Predicate << ";\n";
}
OS << " }\n";
OS << "}\n\n";
Expand Down Expand Up @@ -1134,41 +1133,19 @@ bool DecoderTableBuilder::emitPredicateMatchAux(const Init &Val,
return true;
}
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sorry, missed it. emitPredicateMatchAux is now unused.


// Returns true if there was any predicate emitted.
bool DecoderTableBuilder::emitPredicateMatch(raw_ostream &OS,
unsigned EncodingID) const {
const ListInit *Predicates =
Encodings[EncodingID].getRecord()->getValueAsListInit("Predicates");
bool IsFirstEmission = true;
for (unsigned i = 0; i < Predicates->size(); ++i) {
const Record *Pred = Predicates->getElementAsRecord(i);
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;

if (!isa<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
continue;

if (!IsFirstEmission)
OS << " && ";
if (emitPredicateMatchAux(*Pred->getValueAsDag("AssemblerCondDag"),
Predicates->size() > 1, OS))
PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
IsFirstEmission = false;
}
return !Predicates->empty();
}

bool DecoderTableBuilder::doesOpcodeNeedPredicate(unsigned EncodingID) const {
const ListInit *Predicates =
Encodings[EncodingID].getRecord()->getValueAsListInit("Predicates");
for (unsigned i = 0; i < Predicates->size(); ++i) {
const Record *Pred = Predicates->getElementAsRecord(i);
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;

if (isa<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
return true;
}
return false;
std::vector<const Record *> Predicates =
Encodings[EncodingID].getRecord()->getValueAsListOfDefs("Predicates");
auto It = llvm::find_if(Predicates, [](const Record *R) {
return R->getValueAsBit("AssemblerMatcherPredicate");
});
bool AnyAsmPredicate = It != Predicates.end();
if (!AnyAsmPredicate)
return false;
SubtargetFeatureInfo::emitMCPredicateCheck(OS, Target.getName(), Predicates);
return true;
}

unsigned DecoderTableBuilder::getPredicateIndex(StringRef Predicate) const {
Expand All @@ -1186,15 +1163,11 @@ unsigned DecoderTableBuilder::getPredicateIndex(StringRef Predicate) const {
}

void DecoderTableBuilder::emitPredicateTableEntry(unsigned EncodingID) const {
if (!doesOpcodeNeedPredicate(EncodingID))
return;

// Build up the predicate string.
SmallString<256> Predicate;
// FIXME: emitPredicateMatch() functions can take a buffer directly rather
// than a stream.
raw_svector_ostream PS(Predicate);
emitPredicateMatch(PS, EncodingID);
if (!emitPredicateMatch(PS, EncodingID))
return;

// Figure out the index into the predicate table for the predicate just
// computed.
Expand Down