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16 changes: 8 additions & 8 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -403,12 +403,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Legal);
}

if (Subtarget.hasStdExtZbb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
if (Subtarget.hasCTZLike()) {
if (Subtarget.is64Bit())
setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTTZ, XLenVT, Expand);
}

if (!Subtarget.hasCPOPLike()) {
// TODO: These should be set to LibCall, but this currently breaks
// the Linux kernel build. See #101786. Lacks i128 tests, too.
if (Subtarget.is64Bit())
Expand All @@ -418,8 +420,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
}

if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
if (Subtarget.hasCLZLike()) {
// We need the custom lowering to make sure that the resulting sequence
// for the 32bit case is efficient on 64bit targets.
// Use default promotion for i32 without Zbb.
Expand Down Expand Up @@ -2158,13 +2159,11 @@ bool RISCVTargetLowering::signExtendConstant(const ConstantInt *CI) const {
}

bool RISCVTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
return Subtarget.hasStdExtZbb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit());
return Subtarget.hasCTZLike();
}

bool RISCVTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit());
return Subtarget.hasCLZLike();
}

bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
Expand Down Expand Up @@ -24843,6 +24842,7 @@ bool RISCVTargetLowering::isCtpopFast(EVT VT) const {
return isTypeLegal(VT) && Subtarget.hasStdExtZvbb();
if (VT.isFixedLengthVector() && Subtarget.hasStdExtZvbb())
return true;
// FIXME: Should use hasCPOPLike here.
return Subtarget.hasStdExtZbb() &&
(VT == MVT::i32 || VT == MVT::i64 || VT.isFixedLengthVector());
}
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -186,6 +186,17 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return HasStdExtZfhmin || HasStdExtZfbfmin;
}

bool hasCLZLike() const {
return HasStdExtZbb || HasVendorXTHeadBb ||
(HasVendorXCVbitmanip && !IsRV64);
}
bool hasCTZLike() const {
return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
}
bool hasCPOPLike() const {
return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
}

bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }

bool hasCZEROLike() const {
Expand Down