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CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo #158224

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27e24b9
CodeGen: Remove MachineFunction argument from getPointerRegClass
arsenm Sep 11, 2025
ce9fb44
CodeGen: Remove MachineFunction argument from getRegClass
arsenm Aug 24, 2025
532af14
CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo
arsenm Sep 12, 2025
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18 changes: 11 additions & 7 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
: CallFrameSetupOpcode(CFSetupOpcode),
const TargetRegisterInfo &TRI;

TargetInstrInfo(const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u,
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Or should the argument be TargetSubtargetInfo?

unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u,
unsigned ReturnOpcode = ~0u)
: TRI(TRI), CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}

Expand All @@ -124,6 +127,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();

const TargetRegisterInfo &getRegisterInfo() const { return TRI; }

static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;
}
Expand All @@ -135,10 +140,9 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {

/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.
virtual
const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
const TargetRegisterInfo *TRI,
const MachineFunction &MF) const;
virtual const TargetRegisterClass *
getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
const TargetRegisterInfo *TRI) const;

/// Returns true if MI is an instruction we are unable to reason about
/// (like a call or something with unmodeled side effects).
Expand Down
2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/TargetRegisterInfo.h
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Expand Up @@ -883,7 +883,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// If a target supports multiple different pointer register classes,
/// kind specifies which one is indicated.
virtual const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
getPointerRegClass(unsigned Kind = 0) const {
llvm_unreachable("Target didn't implement getPointerRegClass!");
}

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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
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Expand Up @@ -395,7 +395,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// Note register reference...
const TargetRegisterClass *RC = nullptr;
if (i < MI.getDesc().getNumOperands())
RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
RC = TII->getRegClass(MI.getDesc(), i, TRI);
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
RegRefs.emplace(Reg.asMCReg(), RR);
}
Expand Down Expand Up @@ -479,7 +479,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
// Note register reference...
const TargetRegisterClass *RC = nullptr;
if (i < MI.getDesc().getNumOperands())
RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
RC = TII->getRegClass(MI.getDesc(), i, TRI);
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
RegRefs.emplace(Reg.asMCReg(), RR);
}
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/BreakFalseDeps.cpp
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Expand Up @@ -133,8 +133,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
}

// Get the undef operand's register class
const TargetRegisterClass *OpRC =
TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
const TargetRegisterClass *OpRC = TII->getRegClass(MI->getDesc(), OpIdx, TRI);
assert(OpRC && "Not a valid register class");

// If the instruction has a true dependency, we can hide the false depdency
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
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Expand Up @@ -187,7 +187,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
const TargetRegisterClass *NewRC = nullptr;

if (i < MI.getDesc().getNumOperands())
NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
NewRC = TII->getRegClass(MI.getDesc(), i, TRI);

// For now, only allow the register to be changed if its register
// class is consistent across all uses.
Expand Down Expand Up @@ -316,7 +316,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {

const TargetRegisterClass *NewRC = nullptr;
if (i < MI.getDesc().getNumOperands())
NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
NewRC = TII->getRegClass(MI.getDesc(), i, TRI);

// For now, only allow the register to be changed if its register
// class is consistent across all uses.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Expand Up @@ -1863,7 +1863,7 @@ bool IRTranslator::translateVectorDeinterleave2Intrinsic(
void IRTranslator::getStackGuard(Register DstReg,
MachineIRBuilder &MIRBuilder) {
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
MRI->setRegClass(DstReg, TRI->getPointerRegClass());
auto MIB =
MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/Utils.cpp
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Expand Up @@ -114,7 +114,7 @@ Register llvm::constrainOperandRegClass(
// Assume physical registers are properly constrained.
assert(Reg.isVirtual() && "PhysReg not implemented");

const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI);
// Some of the target independent instructions, like COPY, may not impose any
// register class constraints on some of their operands: If it's a use, we can
// skip constraining as the instruction defining the register would constrain
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/InitUndef.cpp
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Expand Up @@ -232,7 +232,7 @@ bool InitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
MachineOperand &UseMO = MI.getOperand(UseOpIdx);
if (UseMO.getReg() == MCRegister::NoRegister) {
const TargetRegisterClass *RC =
TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
TII->getRegClass(MI.getDesc(), UseOpIdx, TRI);
Register NewDest = MRI->createVirtualRegister(RC);
// We don't have a way to update dead lanes, so keep track of the
// new register so that we avoid querying it later.
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/CodeGen/MachineInstr.cpp
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Expand Up @@ -976,11 +976,9 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
const TargetRegisterInfo *TRI) const {
assert(getParent() && "Can't have an MBB reference here!");
assert(getMF() && "Can't have an MF reference here!");
const MachineFunction &MF = *getMF();

// Most opcodes have fixed constraints in their MCInstrDesc.
if (!isInlineAsm())
return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
return TII->getRegClass(getDesc(), OpIdx, TRI);

if (!getOperand(OpIdx).isReg())
return nullptr;
Expand All @@ -1003,7 +1001,7 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,

// Assume that all registers in a memory operand are pointers.
if (F.isMemKind())
return TRI->getPointerRegClass(MF);
return TRI->getPointerRegClass();

return nullptr;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineLICM.cpp
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Expand Up @@ -1420,7 +1420,7 @@ MachineInstr *MachineLICMImpl::ExtractHoistableLoad(MachineInstr *MI,
if (NewOpc == 0) return nullptr;
const MCInstrDesc &MID = TII->get(NewOpc);
MachineFunction &MF = *MI->getMF();
const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
// Ok, we're unfolding. Create a temporary register and do the unfold.
Register Reg = MRI->createVirtualRegister(RC);

Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Expand Up @@ -2636,7 +2636,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (MONum < MCID.getNumOperands()) {
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
TII->getRegClass(MCID, MONum, TRI)) {
if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum);
OS << printReg(Reg, TRI) << " is not a "
Expand Down Expand Up @@ -2721,11 +2721,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// comply to it.
if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
MONum < MCID.getNumOperands() &&
TII->getRegClass(MCID, MONum, TRI, *MF)) {
TII->getRegClass(MCID, MONum, TRI)) {
report("Virtual register does not match instruction constraint", MO,
MONum);
OS << "Expect register class "
<< TRI->getRegClassName(TII->getRegClass(MCID, MONum, TRI, *MF))
<< TRI->getRegClassName(TII->getRegClass(MCID, MONum, TRI))
<< " but got nothing\n";
return;
}
Expand All @@ -2752,7 +2752,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (MONum < MCID.getNumOperands()) {
if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) {
TII->getRegClass(MCID, MONum, TRI)) {
if (SubIdx) {
const TargetRegisterClass *SuperRC =
TRI->getLargestLegalSuperClass(RC, *MF);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/RegisterCoalescer.cpp
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Expand Up @@ -1374,7 +1374,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
}

const unsigned DefSubIdx = DefMI->getOperand(0).getSubReg();
const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI);
if (!DefMI->isImplicitDef()) {
if (DstReg.isPhysical()) {
Register NewDstReg = DstReg;
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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Expand Up @@ -1964,8 +1964,7 @@ Register FastISel::createResultReg(const TargetRegisterClass *RC) {
Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op,
unsigned OpNum) {
if (Op.isVirtual()) {
const TargetRegisterClass *RegClass =
TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
const TargetRegisterClass *RegClass = TII.getRegClass(II, OpNum, &TRI);
if (!MRI.constrainRegClass(Op, RegClass)) {
// If it's not legal to COPY between the register classes, something
// has gone very wrong before we got here.
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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Expand Up @@ -125,7 +125,7 @@ void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
const TargetRegisterClass *RC = nullptr;
if (i + II.getNumDefs() < II.getNumOperands()) {
RC = TRI->getAllocatableClass(
TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF));
TII->getRegClass(II, i + II.getNumDefs(), TRI));
}
if (!UseRC)
UseRC = RC;
Expand Down Expand Up @@ -197,7 +197,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
// register instead of creating a new vreg.
Register VRBase;
const TargetRegisterClass *RC =
TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
TRI->getAllocatableClass(TII->getRegClass(II, i, TRI));
// Always let the value type influence the used register class. The
// constraints on the instruction may be too lax to represent the value
// type correctly. For example, a 64-bit float (X86::FR64) can't live in
Expand Down Expand Up @@ -330,7 +330,7 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
if (II) {
const TargetRegisterClass *OpRC = nullptr;
if (IIOpNum < II->getNumOperands())
OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
OpRC = TII->getRegClass(*II, IIOpNum, TRI);

if (OpRC) {
unsigned MinNumRegs = MinRCSize;
Expand Down Expand Up @@ -409,7 +409,7 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
Register VReg = R->getReg();
MVT OpVT = Op.getSimpleValueType();
const TargetRegisterClass *IIRC =
II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI))
: nullptr;
const TargetRegisterClass *OpRC =
TLI->isTypeLegal(OpVT)
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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Expand Up @@ -340,7 +340,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,

unsigned Idx = RegDefPos.GetIdx();
const MCInstrDesc &Desc = TII->get(Opcode);
const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
assert(RC && "Not a valid register class");
RegClass = RC->getID();
// FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
Expand Down
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