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Parent: ARM: Remove TRI argument from AddDReg
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CodeGen: Remove TRI arguments from stack load/store hooks #158240

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6 changes: 2 additions & 4 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1165,8 +1165,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// register spill instruction, part of prologue, during the frame lowering.
virtual void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::storeRegToStackSlot!");
Expand All @@ -1184,8 +1183,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// register reload instruction, part of epilogue, during the frame lowering.
virtual void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::loadRegFromStackSlot!");
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
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Expand Up @@ -420,7 +420,7 @@ class StatepointState {

LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore);
TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
RC, &TRI, Register());
RC, Register());
}
}

Expand All @@ -429,15 +429,15 @@ class StatepointState {
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
int FI = RegToSlotIdx[Reg];
if (It != MBB->end()) {
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
return;
}

// To insert reload at the end of MBB, insert it before last instruction
// and then swap them.
assert(!MBB->empty() && "Empty block");
--It;
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
MachineInstr *Reload = It->getPrevNode();
int Dummy = 0;
(void)Dummy;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/InlineSpiller.cpp
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Expand Up @@ -473,7 +473,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
MachineInstrSpan MIS(MII, MBB);
// Insert spill without kill flag immediately after def.
TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
MRI.getRegClass(SrcReg), &TRI, Register());
MRI.getRegClass(SrcReg), Register());
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
getVDefInterval(MI, LIS);
Expand Down Expand Up @@ -1098,7 +1098,7 @@ void InlineSpiller::insertReload(Register NewVReg,

MachineInstrSpan MIS(MI, &MBB);
TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
MRI.getRegClass(NewVReg), &TRI, Register());
MRI.getRegClass(NewVReg), Register());

LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);

Expand Down Expand Up @@ -1134,7 +1134,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool isKill,

if (IsRealSpill)
TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot,
MRI.getRegClass(NewVReg), &TRI, Register());
MRI.getRegClass(NewVReg), Register());
else
// Don't spill undef value.
// Anything works for undef, in particular keeping the memory
Expand Down Expand Up @@ -1708,7 +1708,7 @@ void HoistSpillHelper::hoistAllSpills() {
MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, *BB);
MachineInstrSpan MIS(MII, BB);
TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot,
MRI.getRegClass(LiveReg), &TRI, Register());
MRI.getRegClass(LiveReg), Register());
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
getVDefInterval(MI, LIS);
Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/CodeGen/RegAllocFast.cpp
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Expand Up @@ -594,8 +594,7 @@ void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before,
LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');

const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI,
VirtReg);
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, VirtReg);
++NumStores;

MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator();
Expand Down Expand Up @@ -652,7 +651,7 @@ void RegAllocFastImpl::reload(MachineBasicBlock::iterator Before,
<< printReg(PhysReg, TRI) << '\n');
int FI = getStackSpaceFor(VirtReg);
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, VirtReg);
++NumLoads;
}

Expand Down Expand Up @@ -1123,7 +1122,7 @@ bool RegAllocFastImpl::defineVirtReg(MachineInstr &MI, unsigned OpNum,
if (MO.isMBB()) {
MachineBasicBlock *Succ = MO.getMBB();
TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
&RC, TRI, VirtReg);
&RC, VirtReg);
++NumStores;
Succ->addLiveIn(PhysReg);
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RegisterScavenging.cpp
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Expand Up @@ -276,14 +276,14 @@ RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
": Cannot scavenge register without an emergency "
"spill slot!");
}
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register());
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, Register());
MachineBasicBlock::iterator II = std::prev(Before);

unsigned FIOperandNum = getFrameIndexOperandNum(*II);
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);

// Restore the scavenged register before its use (or first terminator).
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register());
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, Register());
II = std::prev(UseMI);

FIOperandNum = getFrameIndexOperandNum(*II);
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
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Expand Up @@ -198,7 +198,7 @@ void TargetFrameLowering::spillCalleeSavedRegister(
} else {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII->storeRegToStackSlot(SaveBlock, MI, Reg, true, CS.getFrameIdx(), RC,
TRI, Register());
Register());
}
}

Expand All @@ -212,8 +212,7 @@ void TargetFrameLowering::restoreCalleeSavedRegister(
.addReg(CS.getDstReg(), getKillRegState(true));
} else {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
Register());
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, Register());
assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
}
}
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
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Expand Up @@ -792,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
// code.
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
} else {
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC,
Register());
}
} else
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, Register());

return &*--Pos;
}
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Expand Up @@ -3732,7 +3732,7 @@ struct ScopedScavengeOrSpill {
}
FreeReg = SpillCandidate;
SpillFI = MaybeSpillFI->value();
TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC, &TRI,
TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC,
Register());
}

Expand All @@ -3745,8 +3745,7 @@ struct ScopedScavengeOrSpill {

~ScopedScavengeOrSpill() {
if (hasSpilled())
TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, &TRI,
Register());
TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, Register());
}

private:
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -5565,7 +5565,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
Register VReg,
MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
Expand All @@ -5579,7 +5578,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
bool Offset = true;
MCRegister PNRReg = MCRegister::NoRegister;
unsigned StackID = TargetStackID::Default;
switch (TRI->getSpillSize(*RC)) {
switch (RI.getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::STRBui;
Expand Down Expand Up @@ -5747,10 +5746,12 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
.addMemOperand(MMO);
}

void AArch64InstrInfo::loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
Register VReg, MachineInstr::MIFlag Flags) const {
void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
Register DestReg, int FI,
const TargetRegisterClass *RC,
Register VReg,
MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
Expand All @@ -5762,7 +5763,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
bool Offset = true;
unsigned StackID = TargetStackID::Default;
Register PNRReg = MCRegister::NoRegister;
switch (TRI->getSpillSize(*RC)) {
switch (TRI.getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRBui;
Expand Down Expand Up @@ -6394,10 +6395,10 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
"Mismatched register size in non subreg COPY");
if (IsSpill)
storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
getRegClass(SrcReg), &TRI, Register());
getRegClass(SrcReg), Register());
else
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
getRegClass(DstReg), &TRI, Register());
getRegClass(DstReg), Register());
return &*--InsertPt;
}

Expand All @@ -6415,8 +6416,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
assert(SrcMO.getSubReg() == 0 &&
"Unexpected subreg on physical register");
storeRegToStackSlot(MBB, InsertPt, AArch64::XZR, SrcMO.isKill(),
FrameIndex, &AArch64::GPR64RegClass, &TRI,
Register());
FrameIndex, &AArch64::GPR64RegClass, Register());
return &*--InsertPt;
}

Expand Down Expand Up @@ -6450,7 +6450,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
TRI.getRegSizeInBits(*FillRC) &&
"Mismatched regclass size on folded subreg COPY");
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI,
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC,
Register());
MachineInstr &LoadMI = *--InsertPt;
MachineOperand &LoadDst = LoadMI.getOperand(0);
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.h
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Expand Up @@ -353,14 +353,13 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {

void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;

void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;

// This tells target independent code that it is okay to pass instructions
Expand Down
8 changes: 3 additions & 5 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -1694,8 +1694,7 @@ unsigned SIInstrInfo::getVectorRegSpillSaveOpcode(

void SIInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
Expand All @@ -1707,7 +1706,7 @@ void SIInstrInfo::storeRegToStackSlot(
MachineMemOperand *MMO = MF->getMachineMemOperand(
PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
FrameInfo.getObjectAlign(FrameIndex));
unsigned SpillSize = TRI->getSpillSize(*RC);
unsigned SpillSize = RI.getSpillSize(*RC);

MachineRegisterInfo &MRI = MF->getRegInfo();
if (RI.isSGPRClass(RC)) {
Expand Down Expand Up @@ -1889,14 +1888,13 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
Register VReg,
MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
const DebugLoc &DL = MBB.findDebugLoc(MI);
unsigned SpillSize = TRI->getSpillSize(*RC);
unsigned SpillSize = RI.getSpillSize(*RC);

MachinePointerInfo PtrInfo
= MachinePointerInfo::getFixedStack(*MF, FrameIndex);
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -302,14 +302,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {

void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;

void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg,
int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;

bool expandPostRAPseudo(MachineInstr &MI) const override;
Expand Down
9 changes: 4 additions & 5 deletions llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
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Expand Up @@ -117,27 +117,26 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
MachineFunction &MF = *SaveBlock.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *RI = ST.getRegisterInfo();

MachineBasicBlock::iterator I = SaveBlock.begin();
if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, RI)) {
for (const CalleeSavedInfo &CS : CSI) {
// Insert the spill to the stack frame.
MCRegister Reg = CS.getReg();

MachineInstrSpan MIS(I, &SaveBlock);
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(
const TargetRegisterClass *RC = RI->getMinimalPhysRegClass(
Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);

// If this value was already livein, we probably have a direct use of the
// incoming register value, so don't kill at the spill point. This happens
// since we pass some special inputs (workgroup IDs) in the callee saved
// range.
const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI);
const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, RI);
TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
RC, TRI, Register());
RC, Register());

if (Indexes) {
assert(std::distance(MIS.begin(), I) == 1);
Expand Down
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