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AMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass #158246

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Merged
merged 3 commits into from
Sep 12, 2025
Merged

AMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass #158246

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368a9ed
AMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass
arsenm Sep 5, 2025
f34d220
Remove extra parens
arsenm Sep 12, 2025
bb8f1cd
Update llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
arsenm Sep 12, 2025
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8 changes: 3 additions & 5 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5976,8 +5976,7 @@ SIInstrInfo::getWholeWaveFunctionSetup(MachineFunction &MF) const {
static const TargetRegisterClass *
adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
const MCInstrDesc &TID, unsigned RCID) {
if (!ST.hasGFX90AInsts() && (((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)))) {
if (!ST.hasGFX90AInsts() && (TID.mayLoad() || TID.mayStore())) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
Expand Down Expand Up @@ -6012,10 +6011,9 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
if (OpNum >= TID.getNumOperands())
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) {
// Special pseudos have no alignment requirement
// Special pseudos have no alignment requirement
if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO || isSpill(TID))
return RI.getRegClass(RegClass);
}

return adjustAllocatableRegClass(ST, RI, TID, RegClass);
}
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6 changes: 4 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -797,10 +797,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(Opcode).TSFlags & SIInstrFlags::Spill;
}

static bool isSpill(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::Spill;
static bool isSpill(const MCInstrDesc &Desc) {
return Desc.TSFlags & SIInstrFlags::Spill;
}

static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); }

static bool isWWMRegSpillOpcode(uint16_t Opcode) {
return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
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