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[RISCV] Use hasCPOPLike in isCtpopFast and getPopcntSupport #158371

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Merged
merged 3 commits into from
Sep 12, 2025
Merged

[RISCV] Use hasCPOPLike in isCtpopFast and getPopcntSupport #158371

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07cdaa6
[RISCV] Use hasCPOPLike in getPopcntSupport.
topperc Sep 12, 2025
9342cc5
Pre-commit test
topperc Sep 12, 2025
d827b00
[RISCV] Use hasCPOPLike in isCtpopFast
topperc Sep 12, 2025
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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24844,8 +24844,7 @@ bool RISCVTargetLowering::isCtpopFast(EVT VT) const {
return isTypeLegal(VT) && Subtarget.hasStdExtZvbb();
if (VT.isFixedLengthVector() && Subtarget.hasStdExtZvbb())
return true;
// FIXME: Should use hasCPOPLike here.
return Subtarget.hasStdExtZbb() &&
return Subtarget.hasCPOPLike() &&
(VT == MVT::i32 || VT == MVT::i64 || VT.isFixedLengthVector());
}

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4 changes: 1 addition & 3 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Expand Up @@ -289,9 +289,7 @@ bool RISCVTTIImpl::hasActiveVectorLength() const {
TargetTransformInfo::PopcntSupportKind
RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) const {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
return ST->hasStdExtZbb() || (ST->hasVendorXCVbitmanip() && !ST->is64Bit())
? TTI::PSK_FastHardware
: TTI::PSK_Software;
return ST->hasCPOPLike() ? TTI::PSK_FastHardware : TTI::PSK_Software;
}

InstructionCost RISCVTTIImpl::getPartialReductionCost(
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47 changes: 47 additions & 0 deletions llvm/test/CodeGen/RISCV/xcvbitmanip.ll
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Expand Up @@ -229,3 +229,50 @@ define i32 @test.llvm.bitrev(i32 %a) {
%1 = call i32 @llvm.bitreverse(i32 %a)
ret i32 %1
}

define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {
; CHECK-LABEL: ctpop_i32_ult_two:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.cnt a0, a0
; CHECK-NEXT: sltiu a0, a0, 2
; CHECK-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
%2 = icmp ult i32 %1, 2
ret i1 %2
}

define i1 @ctpop_i32_ugt_one(i32 signext %a) nounwind {
; CHECK-LABEL: ctpop_i32_ugt_one:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.cnt a0, a0
; CHECK-NEXT: sltiu a0, a0, 2
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
%2 = icmp ugt i32 %1, 1
ret i1 %2
}

define i1 @ctpop_i32_eq_one(i32 signext %a) nounwind {
; CHECK-LABEL: ctpop_i32_eq_one:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.cnt a0, a0
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
%2 = icmp eq i32 %1, 1
ret i1 %2
}

define i1 @ctpop_i32_ne_one(i32 signext %a) nounwind {
; CHECK-LABEL: ctpop_i32_ne_one:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.cnt a0, a0
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
%2 = icmp ne i32 %1, 1
ret i1 %2
}
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