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[RISCV] Improve fixed vector handling in isCtpopFast. #158380

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Merged
merged 4 commits into from
Sep 16, 2025
Merged

[RISCV] Improve fixed vector handling in isCtpopFast. #158380

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f7f0da9
Pre-commit test
topperc Sep 12, 2025
96b3422
[RISCV] Improve fixed vector handling in isCtpopFast.
topperc Sep 12, 2025
31163fd
fixup! address review comments
topperc Sep 15, 2025
9b913d9
fixup! Address review comment
topperc Sep 16, 2025
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19 changes: 12 additions & 7 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2752,7 +2752,7 @@ bool RISCVTargetLowering::isLegalElementTypeForRVV(EVT ScalarTy) const {
case MVT::i8:
case MVT::i16:
case MVT::i32:
return true;
return Subtarget.hasVInstructions();
case MVT::i64:
return Subtarget.hasVInstructionsI64();
case MVT::f16:
Expand Down Expand Up @@ -24840,12 +24840,17 @@ bool RISCVTargetLowering::areTwoSDNodeTargetMMOFlagsMergeable(
}

bool RISCVTargetLowering::isCtpopFast(EVT VT) const {
if (VT.isScalableVector())
return isTypeLegal(VT) && Subtarget.hasStdExtZvbb();
if (VT.isFixedLengthVector() && Subtarget.hasStdExtZvbb())
return true;
return Subtarget.hasCPOPLike() &&
(VT == MVT::i32 || VT == MVT::i64 || VT.isFixedLengthVector());
if (VT.isVector()) {
EVT SVT = VT.getVectorElementType();
// If the element type is legal we can use cpop.v if it is enabled.
if (isLegalElementTypeForRVV(SVT))
return Subtarget.hasStdExtZvbb();
// If it will be scalarized, we might be able to use cpop.
return VT.isFixedLengthVector() && Subtarget.hasCPOPLike() &&
(SVT == MVT::i32 || SVT == MVT::i64);
}

return Subtarget.hasCPOPLike() && (VT == MVT::i32 || VT == MVT::i64);
}

unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
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@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB

define void @ctpop_v16i8(ptr %x, ptr %y) {
; CHECK-LABEL: ctpop_v16i8:
Expand Down
20 changes: 12 additions & 8 deletions llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
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Expand Up @@ -18,8 +18,9 @@ define <4 x i1> @test_ult_2(<4 x i64> %x) {
;
; FAST-LABEL: define <4 x i1> @test_ult_2(
; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; FAST-NEXT: [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
; FAST-NEXT: [[CMP1:%.*]] = icmp ult <4 x i64> [[CTPOP]], splat (i64 2)
; FAST-NEXT: [[TMP1:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
; FAST-NEXT: [[TMP2:%.*]] = and <4 x i64> [[X]], [[TMP1]]
; FAST-NEXT: [[CMP1:%.*]] = icmp eq <4 x i64> [[TMP2]], zeroinitializer
; FAST-NEXT: ret <4 x i1> [[CMP1]]
;
%ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
Expand All @@ -37,8 +38,9 @@ define <4 x i1> @test_ugt_1(<4 x i64> %x) {
;
; FAST-LABEL: define <4 x i1> @test_ugt_1(
; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
; FAST-NEXT: [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
; FAST-NEXT: [[CMP1:%.*]] = icmp ugt <4 x i64> [[CTPOP]], splat (i64 1)
; FAST-NEXT: [[TMP1:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
; FAST-NEXT: [[TMP2:%.*]] = and <4 x i64> [[X]], [[TMP1]]
; FAST-NEXT: [[CMP1:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer
; FAST-NEXT: ret <4 x i1> [[CMP1]]
;
%ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
Expand All @@ -56,8 +58,9 @@ define <4 x i1> @test_eq_1(<4 x i64> %x) {
;
; FAST-LABEL: define <4 x i1> @test_eq_1(
; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
; FAST-NEXT: [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
; FAST-NEXT: [[CMP1:%.*]] = icmp eq <4 x i64> [[CTPOP]], splat (i64 1)
; FAST-NEXT: [[TMP1:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
; FAST-NEXT: [[TMP2:%.*]] = xor <4 x i64> [[X]], [[TMP1]]
; FAST-NEXT: [[CMP1:%.*]] = icmp ugt <4 x i64> [[TMP2]], [[TMP1]]
; FAST-NEXT: ret <4 x i1> [[CMP1]]
;
%ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
Expand All @@ -75,8 +78,9 @@ define <4 x i1> @test_ne_1(<4 x i64> %x) {
;
; FAST-LABEL: define <4 x i1> @test_ne_1(
; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
; FAST-NEXT: [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
; FAST-NEXT: [[CMP1:%.*]] = icmp ne <4 x i64> [[CTPOP]], splat (i64 1)
; FAST-NEXT: [[TMP1:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
; FAST-NEXT: [[TMP2:%.*]] = xor <4 x i64> [[X]], [[TMP1]]
; FAST-NEXT: [[CMP1:%.*]] = icmp ule <4 x i64> [[TMP2]], [[TMP1]]
; FAST-NEXT: ret <4 x i1> [[CMP1]]
;
%ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
Expand Down
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