[RISCV] Remove a couple of custom instruction decoders (NFC) #158483
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@llvm/pr-subscribers-backend-risc-v Author: Sergei Barannikov (s-barannikov) ChangesThese instructions can be decoded automatically. Full diff: https://github.com/llvm/llvm-project/pull/158483.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index fb5a35daaf58f..ff07122b61378 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -194,12 +194,24 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X1));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X2));
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(RISCV::X5));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -408,6 +420,18 @@ static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus decodeImmThreeOperand(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createImm(3));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeImmFourOperand(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createImm(4));
+ return MCDisassembler::Success;
+}
+
template <unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
@@ -579,46 +603,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
return decodeZcmpRlist(Inst, Imm, Address, Decoder);
}
-static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint16_t Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
- [[maybe_unused]] DecodeStatus Result =
- DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
- assert(Result == MCDisassembler::Success && "Invalid register");
- return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
- uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
- uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
- uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder)))
- return MCDisassembler::Fail;
- [[maybe_unused]] DecodeStatus Result =
- decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
- assert(Result == MCDisassembler::Success && "Invalid immediate");
-
- // Disassemble the final operand which is implicit.
- unsigned Opcode = Inst.getOpcode();
- bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
- Opcode == RISCV::TH_SWD);
- if (IsWordOp)
- Inst.addOperand(MCOperand::createImm(3));
- else
- Inst.addOperand(MCOperand::createImm(4));
-
- return S;
-}
-
#include "RISCVGenDisassemblerTables.inc"
namespace {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 49c9bdd83d3f6..b37ceaaee9cf4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -44,6 +44,7 @@ def ImmThreeAsmOperand : AsmOperandClass {
def immthree : RISCVOp {
let ParserMatchClass = ImmThreeAsmOperand;
let OperandType = "OPERAND_THREE";
+ let DecoderMethod = "decodeImmThreeOperand";
}
def ImmFourAsmOperand : AsmOperandClass {
@@ -56,6 +57,7 @@ def ImmFourAsmOperand : AsmOperandClass {
def immfour : RISCVOp {
let ParserMatchClass = ImmFourAsmOperand;
let OperandType = "OPERAND_FOUR";
+ let DecoderMethod = "decodeImmFourOperand";
}
//===----------------------------------------------------------------------===//
@@ -161,9 +163,9 @@ class THLoadPair<bits<5> funct5, string opcodestr, Operand consttype>
(ins GPR:$rs1, uimm2:$uimm2, consttype:$const3or4),
opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
bits<2> uimm2;
+ bits<0> const3or4;
let Inst{31-27} = funct5;
let Inst{26-25} = uimm2;
- let DecoderMethod = "decodeXTHeadMemPair";
let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
}
@@ -173,9 +175,9 @@ class THStorePair<bits<5> funct5, string opcodestr, Operand consttype>
(ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, consttype:$const3or4),
opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
bits<2> uimm2;
+ bits<0> const3or4;
let Inst{31-27} = funct5;
let Inst{26-25} = uimm2;
- let DecoderMethod = "decodeXTHeadMemPair";
}
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index 50ebaa9951979..efd06c29dc99f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -12,12 +12,12 @@
class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> {
+ bits<0> rs1;
let Inst{15-13} = 0b011;
let Inst{12} = 0;
let Inst{11-7} = rs1val;
let Inst{6-2} = 0b00000;
let Inst{1-0} = 0b01;
- let DecoderMethod = "decodeCSSPushPopchk";
}
//===----------------------------------------------------------------------===//
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/31078 Here is the relevant piece of the build log for the reference |
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These instructions can be decoded automatically.